# AMC Initialization Sequence

This file was created using the following files on: Thu Oct 29 18:44:46 2015
AMC Version: Major Release: Minor Release:
AMP Version: 3 Major Release: 1 Minor Release: 3
AMC UM Init sourced from: //depot/ip_lib/apple/amcc/trunk.malta/amcc/tb/cfg/static/maqstb_cfg.pl#25
AMP UM Init sourced from: //depot/ip_lib/apple/amp/trunk.malta/amp/tb/cfg/phy_helper_fxns.pl#19

#### Change Log

* ------------------------------------------------------------------
* Version:1 - Files Edited: all
* Initial fiji checkin
* ------------------------------------------------------------------
* Version:6 - herb - Files Edited: maqstb_cfg.pl#8 -
* changes for updated amph V0013 and mcu init gen flow.
* ------------------------------------------------------------------
* Version:7 - rishah - Files Edited: maqs_gen_cfg.pl#7 - maqstb_cfg.pl#13 -
* Ported over changes from Maui B0 related to INIT Sequence.
* ------------------------------------------------------------------
* Version:8 - rishah - Files Edited: phy_helper_fxns.pl#15 -
* Updated MCU init sequence.
* ------------------------------------------------------------------
* Version:9 - cpolapra - Files Edited: maqs_gen_cfg_c.pl#6 -
* Ported over init and calibration changes from Maui A0/B0 and Elba
* ------------------------------------------------------------------
* Version:10 - rishah - Files Edited: phy_helper_fxns.pl#16 -
* Init sequence update for VrefSel for SW Calib.
* ------------------------------------------------------------------

#### 0. AMC Prolog

Program SPLL registers

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
if (platform == ONE_CH_ONE_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050200 ChSelHiBits = 0x5 *read-only ChSelTyp = 0x0 *read-only ChnlStartBit = 0x2 *read-only NumMcuChnl = 0x0
else if (platform == ONE_CH_TWO_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050200 ChSelHiBits = 0x5 *read-only ChSelTyp = 0x0 *read-only ChnlStartBit = 0x2 *read-only NumMcuChnl = 0x0
else if (platform == TWO_CH_TWO_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050210 ChSelHiBits = 0x5 *read-only ChSelTyp = 0x0 *read-only ChnlStartBit = 0x2 *read-only NumMcuChnl = 0x1
else if (platform == TWO_CH_ONE_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050210 ChSelHiBits = 0x5 *read-only ChSelTyp = 0x0 *read-only ChnlStartBit = 0x2 *read-only NumMcuChnl = 0x1
else
amcc_MccLockRegion_mccchnldec = 0x00050220 ChSelHiBits = 0x5 *read-only ChSelTyp = 0x0 *read-only ChnlStartBit = 0x2 *read-only NumMcuChnl = 0x2
| - | - | -
spllctrl_SpllCtrl_ChargePump(n) = 0x00000068 slvpll_cp_boost = 0x0 slvpll_cp_i_set = 0x3 *read-only slvpll_cp_lp = 0x0 *read-only slvpll_cp_md = 0x0 *read-only slvpll_cp_pd = 0x0 *read-only slvpll_cp_r_set = 0x8 *read-only
| - | - | -
spllctrl_SpllCtrl_VCO(n) = 0x00000076 slvpll_vco_buf_pd = 0x0 *read-only slvpll_vco_cap = 0x1 *read-only slvpll_vco_kvco = 0x3 slvpll_vco_pd = 0x0 *read-only slvpll_vco_rv2i = 0x6 *read-only
| - | - | -
spllctrl_SpllCtrl_VCO(n) = 0x00000078 slvpll_vco_buf_pd = 0x0 *read-only slvpll_vco_cap = 0x1 *read-only slvpll_vco_kvco = 0x3 slvpll_vco_pd = 0x0 *read-only slvpll_vco_rv2i = 0x8
| - | - | -
spllctrl_SpllCtrl_LDO(n) = 0x00000004 slvpll_bg_start_sel = 0x0 *read-only slvpll_reg_pd = 0x0 *read-only slvpll_vreg_adj = 0x4
| - | - | -
spllctrl_SpllCtrl_SPLLPwrDnCfg(n) = 0x00000011 bypass_en_stby_pd = 0x1 spll_fast_pd_exit = 0x0 *read-only spll_mode_dcs_pwrdn = 0x1 *read-only use_idle_for_pd = 0x0 *read-only
| - | - | -

#### 1. AMC Initial Configuration

Perform the proper configurations of the AMC. Note that all the timing parameters should be programmed with respect to the normal clock, not the slow boot clock.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

#### Setting up MCU registers and FSP for Freq change

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
amcx_dramcfg_freqchngctl0_freq0(n) = 0x18cd104d freqchngmrw0_addr_freq0 = 0xd freqchngmrw0_ctrl_freq0 = 0x1 freqchngmrw0_data_freq0 = 0x10 freqchngmrw1_addr_freq0 = 0xd freqchngmrw1_ctrl_freq0 = 0x3 freqchngmrw1_data_freq0 = 0x18
| - | - | -
amcx_dramcfg_freqchngctl1_freq0(n) = 0x110c110e freqchngmrw2_addr_freq0 = 0xe freqchngmrw2_ctrl_freq0 = 0x0 freqchngmrw2_data_freq0 = 0x11 freqchngmrw3_addr_freq0 = 0xc freqchngmrw3_ctrl_freq0 = 0x0 freqchngmrw3_data_freq0 = 0x11
| - | - | -
if (platform == FPGA)
amcx_dramcfg_freqchngctl2_freq0(n) = 0xb303000b freqchngmrw4_addr_freq0 = 0xb freqchngmrw4_ctrl_freq0 = 0x0 freqchngmrw4_data_freq0 = 0x0 freqchngmrw5_addr_freq0 = 0x3 freqchngmrw5_ctrl_freq0 = 0x0 freqchngmrw5_data_freq0 = 0xb3
else
amcx_dramcfg_freqchngctl2_freq0(n) = 0xb303440b freqchngmrw4_addr_freq0 = 0xb freqchngmrw4_ctrl_freq0 = 0x0 freqchngmrw4_data_freq0 = 0x44 freqchngmrw5_addr_freq0 = 0x3 freqchngmrw5_ctrl_freq0 = 0x0 freqchngmrw5_data_freq0 = 0xb3
| - | - | -
amcx_dramcfg_freqchngctl3_freq0(n) = 0xce012402 freqchngmrw6_addr_freq0 = 0x2 freqchngmrw6_ctrl_freq0 = 0x0 freqchngmrw6_data_freq0 = 0x24 freqchngmrw7_addr_freq0 = 0x1 freqchngmrw7_ctrl_freq0 = 0x0 freqchngmrw7_data_freq0 = 0xce
| - | - | -
amcx_dramcfg_freqchngctl4_freq0(n) = 0x00000416 freqchngmrw8_addr_freq0 = 0x16 freqchngmrw8_ctrl_freq0 = 0x0 freqchngmrw8_data_freq0 = 0x4 freqchngmrw9_addr_freq0 = 0x0 *read-only freqchngmrw9_ctrl_freq0 = 0x0 *read-only freqchngmrw9_data_freq0 = 0x0 *read-only
| - | - | -
amcx_dramcfg_freqchngtim_freq0(n) = 0x000c1108 freqchngclkofflat_freq0 = 0x8 freqchngclkonlat_freq0 = 0x11 freqchngsocupdlat_freq0 = 0xc
| - | - | -
amcx_dramcfg_freqchngctl0_freq1(n) = 0x18cd104d freqchngmrw0_addr_freq1 = 0xd freqchngmrw0_ctrl_freq1 = 0x1 freqchngmrw0_data_freq1 = 0x10 freqchngmrw1_addr_freq1 = 0xd freqchngmrw1_ctrl_freq1 = 0x3 freqchngmrw1_data_freq1 = 0x18
| - | - | -
amcx_dramcfg_freqchngctl1_freq1(n) = 0x110c110e freqchngmrw2_addr_freq1 = 0xe freqchngmrw2_ctrl_freq1 = 0x0 freqchngmrw2_data_freq1 = 0x11 freqchngmrw3_addr_freq1 = 0xc freqchngmrw3_ctrl_freq1 = 0x0 freqchngmrw3_data_freq1 = 0x11
| - | - | -
if (platform == FPGA)
amcx_dramcfg_freqchngctl2_freq1(n) = 0xf303000b freqchngmrw4_addr_freq1 = 0xb freqchngmrw4_ctrl_freq1 = 0x0 freqchngmrw4_data_freq1 = 0x0 freqchngmrw5_addr_freq1 = 0x3 freqchngmrw5_ctrl_freq1 = 0x0 freqchngmrw5_data_freq1 = 0xf3
else
amcx_dramcfg_freqchngctl2_freq1(n) = 0xf303030b freqchngmrw4_addr_freq1 = 0xb freqchngmrw4_ctrl_freq1 = 0x0 freqchngmrw4_data_freq1 = 0x3 freqchngmrw5_addr_freq1 = 0x3 freqchngmrw5_ctrl_freq1 = 0x0 freqchngmrw5_data_freq1 = 0xf3
| - | - | -
amcx_dramcfg_freqchngctl3_freq1(n) = 0xae015202 freqchngmrw6_addr_freq1 = 0x2 freqchngmrw6_ctrl_freq1 = 0x0 freqchngmrw6_data_freq1 = 0x52 freqchngmrw7_addr_freq1 = 0x1 freqchngmrw7_ctrl_freq1 = 0x0 freqchngmrw7_data_freq1 = 0xae
| - | - | -
amcx_dramcfg_freqchngctl4_freq1(n) = 0x00000416 freqchngmrw8_addr_freq1 = 0x16 freqchngmrw8_ctrl_freq1 = 0x0 freqchngmrw8_data_freq1 = 0x4 freqchngmrw9_addr_freq1 = 0x0 *read-only freqchngmrw9_ctrl_freq1 = 0x0 *read-only freqchngmrw9_data_freq1 = 0x0 *read-only
| - | - | -
amcx_dramcfg_freqchngtim_freq1(n) = 0x000c1108 freqchngclkofflat_freq1 = 0x8 freqchngclkonlat_freq1 = 0x11 freqchngsocupdlat_freq1 = 0xc
| - | - | -
amcx_dramcfg_freqchngctl0_freq2(n) = 0x18cd104d freqchngmrw0_addr_freq2 = 0xd freqchngmrw0_ctrl_freq2 = 0x1 freqchngmrw0_data_freq2 = 0x10 freqchngmrw1_addr_freq2 = 0xd freqchngmrw1_ctrl_freq2 = 0x3 freqchngmrw1_data_freq2 = 0x18
| - | - | -
amcx_dramcfg_freqchngctl1_freq2(n) = 0x590c590e freqchngmrw2_addr_freq2 = 0xe freqchngmrw2_ctrl_freq2 = 0x0 freqchngmrw2_data_freq2 = 0x59 freqchngmrw3_addr_freq2 = 0xc freqchngmrw3_ctrl_freq2 = 0x0 freqchngmrw3_data_freq2 = 0x59
| - | - | -
if (platform == FPGA)
amcx_dramcfg_freqchngctl2_freq2(n) = 0xf303000b freqchngmrw4_addr_freq2 = 0xb freqchngmrw4_ctrl_freq2 = 0x0 freqchngmrw4_data_freq2 = 0x0 freqchngmrw5_addr_freq2 = 0x3 freqchngmrw5_ctrl_freq2 = 0x0 freqchngmrw5_data_freq2 = 0xf3
else
amcx_dramcfg_freqchngctl2_freq2(n) = 0xf303000b freqchngmrw4_addr_freq2 = 0xb freqchngmrw4_ctrl_freq2 = 0x0 freqchngmrw4_data_freq2 = 0x0 freqchngmrw5_addr_freq2 = 0x3 freqchngmrw5_ctrl_freq2 = 0x0 freqchngmrw5_data_freq2 = 0xf3
| - | - | -
amcx_dramcfg_freqchngctl3_freq2(n) = 0x8e010002 freqchngmrw6_addr_freq2 = 0x2 freqchngmrw6_ctrl_freq2 = 0x0 freqchngmrw6_data_freq2 = 0x0 freqchngmrw7_addr_freq2 = 0x1 freqchngmrw7_ctrl_freq2 = 0x0 freqchngmrw7_data_freq2 = 0x8e
| - | - | -
amcx_dramcfg_freqchngctl4_freq2(n) = 0x00000016 freqchngmrw8_addr_freq2 = 0x16 freqchngmrw8_ctrl_freq2 = 0x0 freqchngmrw8_data_freq2 = 0x0 freqchngmrw9_addr_freq2 = 0x0 *read-only freqchngmrw9_ctrl_freq2 = 0x0 *read-only freqchngmrw9_data_freq2 = 0x0 *read-only
| - | - | -
amcx_dramcfg_freqchngtim_freq2(n) = 0x000c1108 freqchngclkofflat_freq2 = 0x8 freqchngclkonlat_freq2 = 0x11 freqchngsocupdlat_freq2 = 0xc
| - | - | -
amcx_dramcfg_freqchngctl0_freq3(n) = 0x18cd104d freqchngmrw0_addr_freq3 = 0xd freqchngmrw0_ctrl_freq3 = 0x1 freqchngmrw0_data_freq3 = 0x10 freqchngmrw1_addr_freq3 = 0xd freqchngmrw1_ctrl_freq3 = 0x3 freqchngmrw1_data_freq3 = 0x18
| - | - | -
amcx_dramcfg_freqchngctl1_freq3(n) = 0x590c590e freqchngmrw2_addr_freq3 = 0xe freqchngmrw2_ctrl_freq3 = 0x0 freqchngmrw2_data_freq3 = 0x59 freqchngmrw3_addr_freq3 = 0xc freqchngmrw3_ctrl_freq3 = 0x0 freqchngmrw3_data_freq3 = 0x59
| - | - | -
if (platform == FPGA)
amcx_dramcfg_freqchngctl2_freq3(n) = 0xf303000b freqchngmrw4_addr_freq3 = 0xb freqchngmrw4_ctrl_freq3 = 0x0 freqchngmrw4_data_freq3 = 0x0 freqchngmrw5_addr_freq3 = 0x3 freqchngmrw5_ctrl_freq3 = 0x0 freqchngmrw5_data_freq3 = 0xf3
else
amcx_dramcfg_freqchngctl2_freq3(n) = 0xf303000b freqchngmrw4_addr_freq3 = 0xb freqchngmrw4_ctrl_freq3 = 0x0 freqchngmrw4_data_freq3 = 0x0 freqchngmrw5_addr_freq3 = 0x3 freqchngmrw5_ctrl_freq3 = 0x0 freqchngmrw5_data_freq3 = 0xf3
| - | - | -
amcx_dramcfg_freqchngctl3_freq3(n) = 0x8e010002 freqchngmrw6_addr_freq3 = 0x2 freqchngmrw6_ctrl_freq3 = 0x0 freqchngmrw6_data_freq3 = 0x0 freqchngmrw7_addr_freq3 = 0x1 freqchngmrw7_ctrl_freq3 = 0x0 freqchngmrw7_data_freq3 = 0x8e
| - | - | -
amcx_dramcfg_freqchngctl4_freq3(n) = 0x00000016 freqchngmrw8_addr_freq3 = 0x16 freqchngmrw8_ctrl_freq3 = 0x0 freqchngmrw8_data_freq3 = 0x0 freqchngmrw9_addr_freq3 = 0x0 *read-only freqchngmrw9_ctrl_freq3 = 0x0 *read-only freqchngmrw9_data_freq3 = 0x0 *read-only
| - | - | -
amcx_dramcfg_freqchngtim_freq3(n) = 0x000c1108 freqchngclkofflat_freq3 = 0x8 freqchngclkonlat_freq3 = 0x11 freqchngsocupdlat_freq3 = 0xc
| - | - | -
ampsdq_ampsdqdllctl_dllupdtctrl(n) = 0x50017350 DllInitUpdtDur = 0x7 *read-only DllUpdtDur = 0x3 *read-only DllUpdtMode = 0x1 DllUpdtPhyUpdtTyp = 0x0 *read-only FreqChangeSDLLUpdDur = 0x50 *read-only SDLLUpdDur = 0x50 *read-only
| - | - | -
ampsca_ampscadllctl_dllupdtctrl(n) = 0x50017350 DllInitUpdtDur = 0x7 *read-only DllUpdtDur = 0x3 *read-only DllUpdtMode = 0x1 DllUpdtPhyUpdtTyp = 0x0 *read-only FreqChangeSDLLUpdDur = 0x50 *read-only SDLLUpdDur = 0x50 *read-only
| - | - | -
| Configure DRAM timing parameters for default frequencyset. Example here shows LPDDR4-2667 8Gb DRAM die. See Section 3.2.2.4 for other value. Configure the PHY timing. These are determined by the design of the PHY and the interface between the PHY and AMC. |
if (platform == FPGA)
amcx_dramtim_lat_freq0(n) = 0x001030c2 DRAMRL_freq0 = 0x3 DRAMWL_freq0 = 0x2 tDQSCKMaxCyc_freq0 = 0x3 *read-only tDQSCKMinCyc_freq0 = 0x0 *read-only tDQSSMaxCyc_freq0 = 0x1 *read-only
else
amcx_dramtim_lat_freq0(n) = 0x00103306 DRAMRL_freq0 = 0xc DRAMWL_freq0 = 0x6 tDQSCKMaxCyc_freq0 = 0x3 *read-only tDQSCKMinCyc_freq0 = 0x0 *read-only tDQSSMaxCyc_freq0 = 0x1 *read-only
| - | - | -
if (platform == FPGA)
amcx_dramtim_lat_freq1(n) = 0x001020c2 DRAMRL_freq1 = 0x3 DRAMWL_freq1 = 0x2 tDQSCKMaxCyc_freq1 = 0x2 *read-only tDQSCKMinCyc_freq1 = 0x0 *read-only tDQSSMaxCyc_freq1 = 0x1 *read-only
else
amcx_dramtim_lat_freq1(n) = 0x00102206 DRAMRL_freq1 = 0x8 DRAMWL_freq1 = 0x6 tDQSCKMaxCyc_freq1 = 0x2 *read-only tDQSCKMinCyc_freq1 = 0x0 *read-only tDQSSMaxCyc_freq1 = 0x1 *read-only
| - | - | -
if (platform == FPGA)
amcx_phytim_phyrdwrtim_freq0(n) = 0x00010d01 PHYRdLat_freq0 = 0xd PHYtPhyWrlat_freq0 = 0x1 PHYtRddataEn_freq0 = 0x1
else
amcx_phytim_phyrdwrtim_freq0(n) = 0x00050d0a PHYRdLat_freq0 = 0xd PHYtPhyWrlat_freq0 = 0x5 PHYtRddataEn_freq0 = 0xa
| - | - | -
if (platform == FPGA)
amcx_phytim_phyrdwrtim_freq1(n) = 0x00010c01 PHYRdLat_freq1 = 0xc PHYtPhyWrlat_freq1 = 0x1 PHYtRddataEn_freq1 = 0x1
else
amcx_phytim_phyrdwrtim_freq1(n) = 0x00050c06 PHYRdLat_freq1 = 0xc PHYtPhyWrlat_freq1 = 0x5 PHYtRddataEn_freq1 = 0x6
| - | - | -
if (platform == FPGA)
amcx_phytim_phyrdwrtim_freq2(n) = 0x00010c01 PHYRdLat_freq2 = 0xc PHYtPhyWrlat_freq2 = 0x1 PHYtRddataEn_freq2 = 0x1
else
amcx_phytim_phyrdwrtim_freq2(n) = 0x00010c01 PHYRdLat_freq2 = 0xc PHYtPhyWrlat_freq2 = 0x1 PHYtRddataEn_freq2 = 0x1
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_caspch_freq0(n) = 0x42110408 tRASCyc_freq0 = 0x11 tRCDCyc_freq0 = 0x8 tRTPCyc_freq0 = 0x4 tWRCyc_freq0 = 0x8 tWTRCyc_freq0 = 0x4
else if (platform == FPGA)
amcx_dramtim_caspch_freq0(n) = 0x40c20402 tRASCyc_freq0 = 0x2 tRCDCyc_freq0 = 0x2 tRTPCyc_freq0 = 0x4 tWRCyc_freq0 = 0x3 tWTRCyc_freq0 = 0x4
else
amcx_dramtim_caspch_freq0(n) = 0x531a060b tRASCyc_freq0 = 0x1a tRCDCyc_freq0 = 0xb tRTPCyc_freq0 = 0x5 tWRCyc_freq0 = 0xc tWTRCyc_freq0 = 0x6
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_act_freq0(n) = 0x10040908 tFAWCyc_freq0 = 0x10 tRPCyc_freq0 = 0x8 tRPabCyc_freq0 = 0x9 tRRDCyc_freq0 = 0x4
else if (platform == FPGA)
amcx_dramtim_act_freq0(n) = 0x01020202 tFAWCyc_freq0 = 0x1 tRPCyc_freq0 = 0x2 tRPabCyc_freq0 = 0x2 tRRDCyc_freq0 = 0x2
else
amcx_dramtim_act_freq0(n) = 0x18060d0b tFAWCyc_freq0 = 0x18 tRPCyc_freq0 = 0xb tRPabCyc_freq0 = 0xd tRRDCyc_freq0 = 0x6
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_autoref_freq0(n) = 0x24480078 tRFCBaseCyc_freq0 = 0x78 *read-only tRFCCyc_freq0 = 0x48 tRFCpbCyc_freq0 = 0x24
else if (platform == FPGA)
amcx_dramtim_autoref_freq0(n) = 0x01010078 tRFCBaseCyc_freq0 = 0x78 *read-only tRFCCyc_freq0 = 0x1 tRFCpbCyc_freq0 = 0x1
else
amcx_dramtim_autoref_freq0(n) = 0x366c0078 tRFCBaseCyc_freq0 = 0x78 *read-only tRFCCyc_freq0 = 0x6c tRFCpbCyc_freq0 = 0x36
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_selfref_freq0(n) = 0x50057012 tFCCyc_freq0 = 0x50 tXSRCyc_freq0 = 0x57 tZQCalCyc_freq0 = 0x12 *read-only
else if (platform == FPGA)
amcx_dramtim_selfref_freq0(n) = 0x28002012 tFCCyc_freq0 = 0x28 tXSRCyc_freq0 = 0x2 tZQCalCyc_freq0 = 0x12 *read-only
else
amcx_dramtim_selfref_freq0(n) = 0x78071012 tFCCyc_freq0 = 0x78 tXSRCyc_freq0 = 0x71 tZQCalCyc_freq0 = 0x12 *read-only
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_modereg(n) = 0x0e0a9084 tMRRCyc = 0x4 tMRRICyc = 0x8 tMRWCyc = 0x9 tVRCGOFFCyc = 0xa tZQLatCyc = 0xe
else if (platform == FPGA)
amcx_dramtim_modereg(n) = 0x060a9024 tMRRCyc = 0x4 tMRRICyc = 0x2 tMRWCyc = 0x9 tVRCGOFFCyc = 0xa tZQLatCyc = 0x6
else
amcx_dramtim_modereg(n) = 0x140a90b4 tMRRCyc = 0x4 tMRRICyc = 0xb tMRWCyc = 0x9 tVRCGOFFCyc = 0xa tZQLatCyc = 0x14
| - | - | -
| Configure DRAM timing parameters for alternative frequency points. For the dynamic frequency change support, all frequency sets should be programmed. See Section 3.2.2.3 for details. The actual values should correspond to the desired frequency points and the actual device specifications. (N=1/2/3) *since mcu_clk freq1 = 200MHz and per-bank refresh is not enabled, mcusch.mifcassch_freq1. HiTempRefRnkAgeOut_freq1 =0x0 |
if (platform == PALLADIUM)
amcx_dramtim_caspch_freq1(n) = 0x42110408 tRASCyc_freq1 = 0x11 tRCDCyc_freq1 = 0x8 tRTPCyc_freq1 = 0x4 tWRCyc_freq1 = 0x8 tWTRCyc_freq1 = 0x4
else if (platform == FPGA)
amcx_dramtim_caspch_freq1(n) = 0x40c20402 tRASCyc_freq1 = 0x2 tRCDCyc_freq1 = 0x2 tRTPCyc_freq1 = 0x4 tWRCyc_freq1 = 0x3 tWTRCyc_freq1 = 0x4
else
amcx_dramtim_caspch_freq1(n) = 0x42110408 tRASCyc_freq1 = 0x11 tRCDCyc_freq1 = 0x8 tRTPCyc_freq1 = 0x4 tWRCyc_freq1 = 0x8 tWTRCyc_freq1 = 0x4
| - | - | -
if (platform == FPGA)
amcx_dramtim_act_freq1(n) = 0x01020202 tFAWCyc_freq1 = 0x1 tRPCyc_freq1 = 0x2 tRPabCyc_freq1 = 0x2 tRRDCyc_freq1 = 0x2
else
amcx_dramtim_act_freq1(n) = 0x10040908 tFAWCyc_freq1 = 0x10 tRPCyc_freq1 = 0x8 tRPabCyc_freq1 = 0x9 tRRDCyc_freq1 = 0x4
| - | - | -
| **IMPORTANT** : For power saving on SOC's using Samsung and Hynix DRAM's, it's mandatory to set autoref_freq1 to 0x1C480050. For SOC's using Micron DRAM, autoref_freq1 should be set to 0x20480050.
if (platform == FPGA)
amcx_dramtim_autoref_freq1(n) = 0x01010050 tRFCBaseCyc_freq1 = 0x50 *read-only tRFCCyc_freq1 = 0x1 tRFCpbCyc_freq1 = 0x1
else
amcx_dramtim_autoref_freq1(n) = 0x24480050 tRFCBaseCyc_freq1 = 0x50 *read-only tRFCCyc_freq1 = 0x48 tRFCpbCyc_freq1 = 0x24
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_selfref_freq1(n) = 0x50057012 tFCCyc_freq1 = 0x50 tXSRCyc_freq1 = 0x57 tZQCalCyc_freq1 = 0x12 *read-only
else if (platform == FPGA)
amcx_dramtim_selfref_freq1(n) = 0x28002012 tFCCyc_freq1 = 0x28 tXSRCyc_freq1 = 0x2 tZQCalCyc_freq1 = 0x12 *read-only
else
amcx_dramtim_selfref_freq1(n) = 0x5004b012 tFCCyc_freq1 = 0x50 tXSRCyc_freq1 = 0x4b tZQCalCyc_freq1 = 0x12 *read-only
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_caspch_freq2(n) = 0x42110408 tRASCyc_freq2 = 0x11 tRCDCyc_freq2 = 0x8 tRTPCyc_freq2 = 0x4 tWRCyc_freq2 = 0x8 tWTRCyc_freq2 = 0x4
else if (platform == FPGA)
amcx_dramtim_caspch_freq2(n) = 0x40c20402 tRASCyc_freq2 = 0x2 tRCDCyc_freq2 = 0x2 tRTPCyc_freq2 = 0x4 tWRCyc_freq2 = 0x3 tWTRCyc_freq2 = 0x4
else
amcx_dramtim_caspch_freq2(n) = 0x40c50402 tRASCyc_freq2 = 0x5 tRCDCyc_freq2 = 0x2 tRTPCyc_freq2 = 0x4 tWRCyc_freq2 = 0x3 tWTRCyc_freq2 = 0x4
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_act_freq2(n) = 0x10040908 tFAWCyc_freq2 = 0x10 tRPCyc_freq2 = 0x8 tRPabCyc_freq2 = 0x9 tRRDCyc_freq2 = 0x4
else if (platform == FPGA)
amcx_dramtim_act_freq2(n) = 0x01020202 tFAWCyc_freq2 = 0x1 tRPCyc_freq2 = 0x2 tRPabCyc_freq2 = 0x2 tRRDCyc_freq2 = 0x2
else
amcx_dramtim_act_freq2(n) = 0x04020302 tFAWCyc_freq2 = 0x4 tRPCyc_freq2 = 0x2 tRPabCyc_freq2 = 0x3 tRRDCyc_freq2 = 0x2
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_autoref_freq2(n) = 0x24480014 tRFCBaseCyc_freq2 = 0x14 *read-only tRFCCyc_freq2 = 0x48 tRFCpbCyc_freq2 = 0x24
else if (platform == FPGA)
amcx_dramtim_autoref_freq2(n) = 0x01010014 tRFCBaseCyc_freq2 = 0x14 *read-only tRFCCyc_freq2 = 0x1 tRFCpbCyc_freq2 = 0x1
else
amcx_dramtim_autoref_freq2(n) = 0x09120014 tRFCBaseCyc_freq2 = 0x14 *read-only tRFCCyc_freq2 = 0x12 tRFCpbCyc_freq2 = 0x9
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_selfref_freq2(n) = 0x50057012 tFCCyc_freq2 = 0x50 tXSRCyc_freq2 = 0x57 tZQCalCyc_freq2 = 0x12 *read-only
else if (platform == FPGA)
amcx_dramtim_selfref_freq2(n) = 0x28002012 tFCCyc_freq2 = 0x28 tXSRCyc_freq2 = 0x2 tZQCalCyc_freq2 = 0x12 *read-only
else
amcx_dramtim_selfref_freq2(n) = 0x28013012 tFCCyc_freq2 = 0x28 tXSRCyc_freq2 = 0x13 tZQCalCyc_freq2 = 0x12 *read-only
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_caspch_freq3(n) = 0x42110408 tRASCyc_freq3 = 0x11 tRCDCyc_freq3 = 0x8 tRTPCyc_freq3 = 0x4 tWRCyc_freq3 = 0x8 tWTRCyc_freq3 = 0x4
else if (platform == FPGA)
amcx_dramtim_caspch_freq3(n) = 0x40c20402 tRASCyc_freq3 = 0x2 tRCDCyc_freq3 = 0x2 tRTPCyc_freq3 = 0x4 tWRCyc_freq3 = 0x3 tWTRCyc_freq3 = 0x4
else
amcx_dramtim_caspch_freq3(n) = 0x40c20402 tRASCyc_freq3 = 0x2 tRCDCyc_freq3 = 0x2 tRTPCyc_freq3 = 0x4 tWRCyc_freq3 = 0x3 tWTRCyc_freq3 = 0x4
| - | - | -
| Process act_freq3 for all platforms |
if (platform == PALLADIUM)
amcx_dramtim_act_freq3(n) = 0x10040b0a tFAWCyc_freq3 = 0x10 tRPCyc_freq3 = 0xa tRPabCyc_freq3 = 0xb tRRDCyc_freq3 = 0x4
else if (platform == FPGA)
amcx_dramtim_act_freq3(n) = 0x01020404 tFAWCyc_freq3 = 0x1 tRPCyc_freq3 = 0x4 tRPabCyc_freq3 = 0x4 tRRDCyc_freq3 = 0x2
else
amcx_dramtim_act_freq3(n) = 0x02020404 tFAWCyc_freq3 = 0x2 tRPCyc_freq3 = 0x4 tRPabCyc_freq3 = 0x4 tRRDCyc_freq3 = 0x2
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_autoref_freq3(n) = 0x24480005 tRFCBaseCyc_freq3 = 0x5 *read-only tRFCCyc_freq3 = 0x48 tRFCpbCyc_freq3 = 0x24
else if (platform == FPGA)
amcx_dramtim_autoref_freq3(n) = 0x01010005 tRFCBaseCyc_freq3 = 0x5 *read-only tRFCCyc_freq3 = 0x1 tRFCpbCyc_freq3 = 0x1
else
amcx_dramtim_autoref_freq3(n) = 0x03050005 tRFCBaseCyc_freq3 = 0x5 *read-only tRFCCyc_freq3 = 0x5 tRFCpbCyc_freq3 = 0x3
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_selfref_freq3(n) = 0x50057012 tFCCyc_freq3 = 0x50 tXSRCyc_freq3 = 0x57 tZQCalCyc_freq3 = 0x12 *read-only
else if (platform == FPGA)
amcx_dramtim_selfref_freq3(n) = 0x28002012 tFCCyc_freq3 = 0x28 tXSRCyc_freq3 = 0x2 tZQCalCyc_freq3 = 0x12 *read-only
else
amcx_dramtim_selfref_freq3(n) = 0x28006012 tFCCyc_freq3 = 0x28 tXSRCyc_freq3 = 0x6 tZQCalCyc_freq3 = 0x12 *read-only
| - | - | -
if (platform == FPGA)
amcx_dramtim_autoref_params(n) = 0x00150013 tREFBWtRFCcnt = 0x15 *read-only tREFICyc = 0x13
else
amcx_dramtim_autoref_params(n) = 0x0015005d tREFBWtRFCcnt = 0x15 *read-only tREFICyc = 0x5d
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_pdn(n) = 0x31263263 tCKECyc = 0x3 tCKEPDECyc = 0x1 *read-only tCKESRCyc = 0x6 tCKEafSRCyc = 0x2 tCKEb4SRCyc = 0x6 tCKafCKECyc = 0x3 tCKb4CKECyc = 0x1 tXPCyc = 0x3
else if (platform == FPGA)
amcx_dramtim_pdn(n) = 0x21262222 tCKECyc = 0x2 tCKEPDECyc = 0x1 *read-only tCKESRCyc = 0x2 tCKEafSRCyc = 0x2 tCKEb4SRCyc = 0x6 tCKafCKECyc = 0x2 tCKb4CKECyc = 0x1 tXPCyc = 0x2
else
amcx_dramtim_pdn(n) = 0x62265295 tCKECyc = 0x5 tCKEPDECyc = 0x1 *read-only tCKESRCyc = 0x9 tCKEafSRCyc = 0x2 tCKEb4SRCyc = 0x6 tCKafCKECyc = 0x6 tCKb4CKECyc = 0x2 tXPCyc = 0x5
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_derate_freq0(n) = 0x28835488 tDQSCKMaxDrtCyc_freq0 = 0x3 tRASDrtCyc_freq0 = 0x12 tRCDDrtCyc_freq0 = 0x8 tRPDrtCyc_freq0 = 0x8 tRPabDrtCyc_freq0 = 0xa tRRDDrtCyc_freq0 = 0x5
else if (platform == FPGA)
amcx_dramtim_derate_freq0(n) = 0x08212082 tDQSCKMaxDrtCyc_freq0 = 0x1 tRASDrtCyc_freq0 = 0x2 tRCDDrtCyc_freq0 = 0x2 tRPDrtCyc_freq0 = 0x2 tRPabDrtCyc_freq0 = 0x2 tRRDDrtCyc_freq0 = 0x2
else
amcx_dramtim_derate_freq0(n) = 0x38c486cc tDQSCKMaxDrtCyc_freq0 = 0x4 tRASDrtCyc_freq0 = 0x1b tRCDDrtCyc_freq0 = 0xc tRPDrtCyc_freq0 = 0xc tRPabDrtCyc_freq0 = 0xe tRRDDrtCyc_freq0 = 0x8
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_derate_freq1(n) = 0x28835488 tDQSCKMaxDrtCyc_freq1 = 0x3 tRASDrtCyc_freq1 = 0x12 tRCDDrtCyc_freq1 = 0x8 tRPDrtCyc_freq1 = 0x8 tRPabDrtCyc_freq1 = 0xa tRRDDrtCyc_freq1 = 0x5
else if (platform == FPGA)
amcx_dramtim_derate_freq1(n) = 0x08212082 tDQSCKMaxDrtCyc_freq1 = 0x1 tRASDrtCyc_freq1 = 0x2 tRCDDrtCyc_freq1 = 0x2 tRPDrtCyc_freq1 = 0x2 tRPabDrtCyc_freq1 = 0x2 tRRDDrtCyc_freq1 = 0x2
else
amcx_dramtim_derate_freq1(n) = 0x28835488 tDQSCKMaxDrtCyc_freq1 = 0x3 tRASDrtCyc_freq1 = 0x12 tRCDDrtCyc_freq1 = 0x8 tRPDrtCyc_freq1 = 0x8 tRPabDrtCyc_freq1 = 0xa tRRDDrtCyc_freq1 = 0x5
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_derate_freq2(n) = 0x28835488 tDQSCKMaxDrtCyc_freq2 = 0x3 tRASDrtCyc_freq2 = 0x12 tRCDDrtCyc_freq2 = 0x8 tRPDrtCyc_freq2 = 0x8 tRPabDrtCyc_freq2 = 0xa tRRDDrtCyc_freq2 = 0x5
else if (platform == FPGA)
amcx_dramtim_derate_freq2(n) = 0x08212082 tDQSCKMaxDrtCyc_freq2 = 0x1 tRASDrtCyc_freq2 = 0x2 tRCDDrtCyc_freq2 = 0x2 tRPDrtCyc_freq2 = 0x2 tRPabDrtCyc_freq2 = 0x2 tRRDDrtCyc_freq2 = 0x2
else
amcx_dramtim_derate_freq2(n) = 0x0c212142 tDQSCKMaxDrtCyc_freq2 = 0x1 tRASDrtCyc_freq2 = 0x5 tRCDDrtCyc_freq2 = 0x2 tRPDrtCyc_freq2 = 0x2 tRPabDrtCyc_freq2 = 0x3 tRRDDrtCyc_freq2 = 0x2
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_derate_freq3(n) = 0x30a35488 tDQSCKMaxDrtCyc_freq3 = 0x3 tRASDrtCyc_freq3 = 0x12 tRCDDrtCyc_freq3 = 0x8 tRPDrtCyc_freq3 = 0xa tRPabDrtCyc_freq3 = 0xc tRRDDrtCyc_freq3 = 0x5
else if (platform == FPGA)
amcx_dramtim_derate_freq3(n) = 0x10412082 tDQSCKMaxDrtCyc_freq3 = 0x1 tRASDrtCyc_freq3 = 0x2 tRCDDrtCyc_freq3 = 0x2 tRPDrtCyc_freq3 = 0x4 tRPabDrtCyc_freq3 = 0x4 tRRDDrtCyc_freq3 = 0x2
else
amcx_dramtim_derate_freq3(n) = 0x10412082 tDQSCKMaxDrtCyc_freq3 = 0x1 tRASDrtCyc_freq3 = 0x2 tRCDDrtCyc_freq3 = 0x2 tRPDrtCyc_freq3 = 0x4 tRPabDrtCyc_freq3 = 0x4 tRRDDrtCyc_freq3 = 0x2
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_lat_freq0(n) = 0x00112306 DRAMRL_freq0 = 0xc DRAMWL_freq0 = 0x6 tDQSCKMaxCyc_freq0 = 0x2 tDQSCKMinCyc_freq0 = 0x1 tDQSSMaxCyc_freq0 = 0x1 *read-only
else if (platform == FPGA)
amcx_dramtim_lat_freq0(n) = 0x001110c2 DRAMRL_freq0 = 0x3 DRAMWL_freq0 = 0x2 tDQSCKMaxCyc_freq0 = 0x1 tDQSCKMinCyc_freq0 = 0x1 tDQSSMaxCyc_freq0 = 0x1 *read-only
else
amcx_dramtim_lat_freq0(n) = 0x00113306 DRAMRL_freq0 = 0xc DRAMWL_freq0 = 0x6 tDQSCKMaxCyc_freq0 = 0x3 tDQSCKMinCyc_freq0 = 0x1 tDQSSMaxCyc_freq0 = 0x1 *read-only
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_lat_freq1(n) = 0x00112206 DRAMRL_freq1 = 0x8 DRAMWL_freq1 = 0x6 tDQSCKMaxCyc_freq1 = 0x2 tDQSCKMinCyc_freq1 = 0x1 tDQSSMaxCyc_freq1 = 0x1 *read-only
else if (platform == FPGA)
amcx_dramtim_lat_freq1(n) = 0x001110c2 DRAMRL_freq1 = 0x3 DRAMWL_freq1 = 0x2 tDQSCKMaxCyc_freq1 = 0x1 tDQSCKMinCyc_freq1 = 0x1 tDQSSMaxCyc_freq1 = 0x1 *read-only
else
amcx_dramtim_lat_freq1(n) = 0x00112206 DRAMRL_freq1 = 0x8 DRAMWL_freq1 = 0x6 tDQSCKMaxCyc_freq1 = 0x2 tDQSCKMinCyc_freq1 = 0x1 tDQSSMaxCyc_freq1 = 0x1 *read-only
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_lat_freq2(n) = 0x001120c2 DRAMRL_freq2 = 0x3 DRAMWL_freq2 = 0x2 tDQSCKMaxCyc_freq2 = 0x2 tDQSCKMinCyc_freq2 = 0x1 tDQSSMaxCyc_freq2 = 0x1 *read-only
else if (platform == FPGA)
amcx_dramtim_lat_freq2(n) = 0x001110c2 DRAMRL_freq2 = 0x3 DRAMWL_freq2 = 0x2 tDQSCKMaxCyc_freq2 = 0x1 tDQSCKMinCyc_freq2 = 0x1 tDQSSMaxCyc_freq2 = 0x1 *read-only
else
amcx_dramtim_lat_freq2(n) = 0x001110c2 DRAMRL_freq2 = 0x3 DRAMWL_freq2 = 0x2 tDQSCKMaxCyc_freq2 = 0x1 tDQSCKMinCyc_freq2 = 0x1 tDQSSMaxCyc_freq2 = 0x1 *read-only
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_lat_freq3(n) = 0x001120c2 DRAMRL_freq3 = 0x3 DRAMWL_freq3 = 0x2 tDQSCKMaxCyc_freq3 = 0x2 tDQSCKMinCyc_freq3 = 0x1 tDQSSMaxCyc_freq3 = 0x1 *read-only
else if (platform == FPGA)
amcx_dramtim_lat_freq3(n) = 0x001110c2 DRAMRL_freq3 = 0x3 DRAMWL_freq3 = 0x2 tDQSCKMaxCyc_freq3 = 0x1 tDQSCKMinCyc_freq3 = 0x1 tDQSSMaxCyc_freq3 = 0x1 *read-only
else
amcx_dramtim_lat_freq3(n) = 0x001110c2 DRAMRL_freq3 = 0x3 DRAMWL_freq3 = 0x2 tDQSCKMaxCyc_freq3 = 0x1 tDQSCKMinCyc_freq3 = 0x1 tDQSSMaxCyc_freq3 = 0x1 *read-only
| - | - | -
if (platform == FPGA)
amcx_dramtim_tat_freq0(n) = 0x01212222 R2rRnkMissTatDeadCyc_freq0 = 0x2 *read-only R2rTatDeadCyc_freq0 = 0x1 *read-only R2wRnkMissTatDeadCyc_freq0 = 0x2 *read-only R2wTatDeadCyc_freq0 = 0x2 W2rRnkMissTatDeadCyc_freq0 = 0x2 *read-only W2wRnkMissTatDeadCyc_freq0 = 0x2 *read-only W2wTatDeadCyc_freq0 = 0x1 *read-only
else
amcx_dramtim_tat_freq0(n) = 0x01312222 R2rRnkMissTatDeadCyc_freq0 = 0x2 *read-only R2rTatDeadCyc_freq0 = 0x1 *read-only R2wRnkMissTatDeadCyc_freq0 = 0x2 *read-only R2wTatDeadCyc_freq0 = 0x3 W2rRnkMissTatDeadCyc_freq0 = 0x2 *read-only W2wRnkMissTatDeadCyc_freq0 = 0x2 *read-only W2wTatDeadCyc_freq0 = 0x1 *read-only
| - | - | -
if (platform == FPGA)
amcx_dramtim_tat_freq1(n) = 0x01212222 R2rRnkMissTatDeadCyc_freq1 = 0x2 *read-only R2rTatDeadCyc_freq1 = 0x1 *read-only R2wRnkMissTatDeadCyc_freq1 = 0x2 *read-only R2wTatDeadCyc_freq1 = 0x2 W2rRnkMissTatDeadCyc_freq1 = 0x2 *read-only W2wRnkMissTatDeadCyc_freq1 = 0x2 *read-only W2wTatDeadCyc_freq1 = 0x1 *read-only
else
amcx_dramtim_tat_freq1(n) = 0x01312222 R2rRnkMissTatDeadCyc_freq1 = 0x2 *read-only R2rTatDeadCyc_freq1 = 0x1 *read-only R2wRnkMissTatDeadCyc_freq1 = 0x2 *read-only R2wTatDeadCyc_freq1 = 0x3 W2rRnkMissTatDeadCyc_freq1 = 0x2 *read-only W2wRnkMissTatDeadCyc_freq1 = 0x2 *read-only W2wTatDeadCyc_freq1 = 0x1 *read-only
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_tat_freq2(n) = 0x01312222 R2rRnkMissTatDeadCyc_freq2 = 0x2 *read-only R2rTatDeadCyc_freq2 = 0x1 *read-only R2wRnkMissTatDeadCyc_freq2 = 0x2 *read-only R2wTatDeadCyc_freq2 = 0x3 W2rRnkMissTatDeadCyc_freq2 = 0x2 *read-only W2wRnkMissTatDeadCyc_freq2 = 0x2 *read-only W2wTatDeadCyc_freq2 = 0x1 *read-only
else
amcx_dramtim_tat_freq2(n) = 0x01212222 R2rRnkMissTatDeadCyc_freq2 = 0x2 *read-only R2rTatDeadCyc_freq2 = 0x1 *read-only R2wRnkMissTatDeadCyc_freq2 = 0x2 *read-only R2wTatDeadCyc_freq2 = 0x2 W2rRnkMissTatDeadCyc_freq2 = 0x2 *read-only W2wRnkMissTatDeadCyc_freq2 = 0x2 *read-only W2wTatDeadCyc_freq2 = 0x1 *read-only
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_tat_freq3(n) = 0x01312222 R2rRnkMissTatDeadCyc_freq3 = 0x2 *read-only R2rTatDeadCyc_freq3 = 0x1 *read-only R2wRnkMissTatDeadCyc_freq3 = 0x2 *read-only R2wTatDeadCyc_freq3 = 0x3 W2rRnkMissTatDeadCyc_freq3 = 0x2 *read-only W2wRnkMissTatDeadCyc_freq3 = 0x2 *read-only W2wTatDeadCyc_freq3 = 0x1 *read-only
else
amcx_dramtim_tat_freq3(n) = 0x01212222 R2rRnkMissTatDeadCyc_freq3 = 0x2 *read-only R2rTatDeadCyc_freq3 = 0x1 *read-only R2wRnkMissTatDeadCyc_freq3 = 0x2 *read-only R2wTatDeadCyc_freq3 = 0x2 W2rRnkMissTatDeadCyc_freq3 = 0x2 *read-only W2wRnkMissTatDeadCyc_freq3 = 0x2 *read-only W2wTatDeadCyc_freq3 = 0x1 *read-only
| - | - | -
amcx_dramcfg_rnkcfg(n) = 0x00006061 Rnk0Odts = 0x6 *read-only Rnk0Valid = 0x1 Rnk1Odts = 0x6 *read-only Rnk1Valid = 0x0 *read-only
| - | - | -
amcx_mifqctrl_mifqmaxctrl_freq0(n) = 0x00000100 HiTempMifQMax_freq0 = 0x0 *read-only MifQMaxAlways = 0x1
| - | - | -
if (platform == FPGA)
amcx_mifqctrl_mifqmaxctrl_freq3(n) = 0x00000003 HiTempMifQMax_freq3 = 0x3
else
amcx_mifqctrl_mifqmaxctrl_freq3(n) = 0x00000001 HiTempMifQMax_freq3 = 0x1
| - | - | -
| Turn off optional power- savingfeatures. This includes dynamic power down, auto self-refresh entry, and clock stopping. |
amcx_dramcfg_pwrmngten(n) = 0x00000000 AutoSR = 0x0 DynPwrDnEn = 0x0 McPhyUpdDramClkOff = 0x0 PwrDnClkOff = 0x0 SRClkOff = 0x0 SRExitOpt = 0x0 *read-only
| - | - | -
| Turn off optional power- savingfeatures. This includes dynamic power down, auto self-refresh entry, and clock stopping. |
amcx_dramcfg_odtszqc(n) = 0x00002000 DerateParamSRExit = 0x1 OdtsRdIntrvl = 0x0 SRExitZQCChnlQuiet = 0x0 *read-only ShareZQRes = 0x0 *read-only TempDrtEn = 0x0 *read-only ZQCChnlQuiet = 0x0 *read-only ZQCStack = 0x0 *read-only ZqCalIntrvl = 0x0 *read-only
| - | - | -
| Turn off transaction scheduling for non- initialization commands |
amcx_amcgen_amcctrl(n) = 0x00000002 McuEn = 0x0 *read-only SchEn = 0x1
| - | - | -
amcx_dramcfg_mcphyupdtparam(n) = 0x15030000 FreqCSettleCyc = 0x5 *read-only McPhyTimeParamCyc = 0x3 *read-only PhyInitStartCyc = 0x0 *read-only PhyUpdMDLL = 0x1 UpdPhyLatCyc = 0x0 *read-only tPhyUpdGap = 0x0 *read-only
| - | - | -
| Program AMC to - wait tXP+2tCK after actual clock changes before valid command - wait 2 cycles after all timing parameter are satisfied before actual clock change - wait indefinitely for AMP to complete handshake. |
amcx_dramcfg_mcphyupdtparam(n) = 0x15030000 FreqCSettleCyc = 0x5 *read-only McPhyTimeParamCyc = 0x3 PhyInitStartCyc = 0x0 PhyUpdMDLL = 0x1 UpdPhyLatCyc = 0x0 *read-only tPhyUpdGap = 0x0 *read-only
| - | - | -

#### 2. AMP Initial Configurations

Perform the proper configurations of the AMP. There are two separate AMP register blocks; the code below must be repeated on both AMP0 and AMP1. (N=0..1)

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| Assert AMP enable |
ampsca_ampscagen_ampen(n) = 0x00000001 AmpEn = 0x1
| - | - | -
| Assert AMP enable |
ampsdq_ampsdqgen_ampen(n) = 0x00000001 AmpEn = 0x1
| - | - | -
ampsca_ampscaiocfg_nondqdspd_f0(n) = 0x000b316b CaDsPd_f0 = 0xb Ck0DsPd_f0 = 0xb Ck1DsPd_f0 = 0xc *read-only CsDsPd_f0 = 0xb
| - | - | -
ampsca_ampscaiocfg_nondqdspd_f1(n) = 0x000b216b CaDsPd_f1 = 0xb Ck0DsPd_f1 = 0xb Ck1DsPd_f1 = 0x8 *read-only CsDsPd_f1 = 0xb
| - | - | -
ampsca_ampscaiocfg_nondqdspd_f2(n) = 0x000b3d6b CaDsPd_f2 = 0xb Ck0DsPd_f2 = 0xb Ck1DsPd_f2 = 0xf *read-only CsDsPd_f2 = 0xb
| - | - | -
ampsca_ampscaiocfg_nondqdspd_f3(n) = 0x000b3d6b CaDsPd_f3 = 0xb Ck0DsPd_f3 = 0xb Ck1DsPd_f3 = 0xf *read-only CsDsPd_f3 = 0xb
| - | - | -
ampsca_ampscaiocfg_nondqds_f1(n) = 0x00080508 CaDs_f1 = 0x8 Ck0Ds_f1 = 0x8 Ck1Ds_f1 = 0x1 *read-only CsDs_f1 = 0x8
| - | - | -
ampsca_ampscaiocfg_nondqds_f2(n) = 0x00083d08 CaDs_f2 = 0x8 Ck0Ds_f2 = 0x8 Ck1Ds_f2 = 0xf *read-only CsDs_f2 = 0x8
| - | - | -
ampsca_ampscaiocfg_nondqds_f3(n) = 0x00083d08 CaDs_f3 = 0x8 Ck0Ds_f3 = 0x8 Ck1Ds_f3 = 0xf *read-only CsDs_f3 = 0x8
| - | - | -
ampsca_ampscaiocfg_CaCkCsWkDs(n) = 0x000000db CaWkDs = 0x3 CkWkDs = 0x3 CsWkDs = 0x3
| - | - | -
ampsca_ampscaodt_VRef_f0(n) = 0x00000003 VRefSel = 0x3
| - | - | -
ampsca_ampscaodt_VRef_f1(n) = 0x00000003 VRefSel = 0x3
| - | - | -
ampsca_ampscaodt_VRef_f2(n) = 0x00000003 VRefSel = 0x3
| - | - | -
ampsca_ampscaodt_VRef_f3(n) = 0x00000003 VRefSel = 0x3
| - | - | -
| ODTEnable_f0 |
if (platform == PALLADIUM)
ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000000 ODTEnable = 0x0
else if (platform == FPGA)
ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000000 ODTEnable = 0x0
else
ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000001 ODTEnable = 0x1
| - | - | -
| ODTEnable_f1 |
if (platform == PALLADIUM)
ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000000 ODTEnable = 0x0
else if (platform == FPGA)
ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000000 ODTEnable = 0x0
else
ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000001 ODTEnable = 0x1
| - | - | -
| ODTEnable_f3 |
ampsca_ampscaodt_ODTEnable_f3(n) = 0x00000000 ODTEnable = 0x0
| - | - | -
ampsdq_ampsdqiocfg_dqds_f0(n) = 0x000c0b08 RdDqODTDs = 0xc WrDqPdDs = 0xb WrDqPuDs = 0x8
| - | - | -
ampsdq_ampsdqiocfg_dqds_f1(n) = 0x00080b00 RdDqODTDs = 0x8 WrDqPdDs = 0xb WrDqPuDs = 0x0
| - | - | -
ampsdq_ampsdqiocfg_dqds_f2(n) = 0x00080b00 RdDqODTDs = 0x8 WrDqPdDs = 0xb WrDqPuDs = 0x0
| - | - | -
ampsdq_ampsdqiocfg_dqds_f3(n) = 0x00080b00 RdDqODTDs = 0x8 WrDqPdDs = 0xb WrDqPuDs = 0x0
| - | - | -
ampsdq_ampsdqiocfg_dqdqsds_f0(n) = 0x000c0b08 RdDqDqsODTDs = 0xc WrDqDqsPdDs = 0xb WrDqDqsPuDs = 0x8
| - | - | -
ampsdq_ampsdqiocfg_dqdqsds_f1(n) = 0x00080b00 RdDqDqsODTDs = 0x8 WrDqDqsPdDs = 0xb WrDqDqsPuDs = 0x0
| - | - | -
ampsdq_ampsdqiocfg_dqdqsds_f2(n) = 0x00080b00 RdDqDqsODTDs = 0x8 WrDqDqsPdDs = 0xb WrDqDqsPuDs = 0x0
| - | - | -
ampsdq_ampsdqiocfg_dqdqsds_f3(n) = 0x00080b00 RdDqDqsODTDs = 0x8 WrDqDqsPdDs = 0xb WrDqDqsPuDs = 0x0
| - | - | -
ampsdq_ampsdqodt_VRef_f0(n) = 0x00c000c0 DqsVRefSel = 0xc0 VRefSel = 0xc0
| - | - | -
ampsdq_ampsdqodt_VRef_f1(n) = 0x00c000c0 DqsVRefSel = 0xc0 VRefSel = 0xc0
| - | - | -
ampsdq_ampsdqodt_VRef_f2(n) = 0x00800080 DqsVRefSel = 0x80 VRefSel = 0x80
| - | - | -
ampsdq_ampsdqodt_VRef_f3(n) = 0x00800080 DqsVRefSel = 0x80 VRefSel = 0x80
| - | - | -
ampsdq_ampsdqrdtim_dqspdres(n) = 0x00000001 DqsPdVal = 0x1 *read-only DqsWkPuPdVal = 0x0
| - | - | -
ampsca_ampscasdllctrl_SDLLUpdateCtrl(n) = 0x0303030b ClkEn2Valid = 0x3 *read-only ReqWaitDelay = 0xb Valid2ClkEn = 0x3 *read-only ValidLen = 0x3 *read-only
| - | - | -
ampsdq_ampsdqsdllctrl_SDLLUpdateCtrl(n) = 0x0003000b ClkEn2Valid = 0x0 *read-only ReqWaitDelay = 0xb Valid2ClkEn = 0x0 *read-only ValidLen = 0x3 *read-only
| - | - | -
ampsdq_ampsdqsdllctrl_rd0sdllctrl(n) = 0x00ff0004 Rd0RunSDLLUpd = 0x0 *read-only Rd0RunSDLLUpdOverride = 0x0 *read-only Rd0RunSDLLUpdWrResult = 0x0 *read-only Rd0SDLLOvrVal = 0xff
| - | - | -
| Poll ampsdqsdllctrl rd0sdllctrl |
Poll: ampsdqsdllctrl_rd0sdllctrl Rd0RunSDLLUpdWrResult while((CSR(ampsdq_ampsdqsdllctrl_rd0sdllctrl(n)) & 0x4) != 0x0)
| - | - | -
ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000004 WrDqDqsRunSDLLUpd = 0x0 *read-only WrDqDqsRunSDLLUpdOverride = 0x0 *read-only WrDqDqsRunSDLLUpdWrResult = 0x0 *read-only WrDqDqsWrLvlReBalanceEn = 0x0 *read-only WrDqSDLLAddHalfClk_f0 = 0x0 *read-only WrDqSDLLAddHalfClk_f1 = 0x0 *read-only WrDqSDLLAddHalfClk_f2 = 0x0 *read-only WrDqSDLLAddHalfClk_f3 = 0x0 *read-only WrDqSDLLHalfClkEn = 0x0 *read-only WrDqSDLLOvrVal = 0x0 WrDqsSDLLOvrVal = 0xff
| - | - | -
| Poll ampsdqsdllctrl WrDqDqsSDLLCtrl |
Poll: ampsdqsdllctrl_WrDqDqsSDLLCtrl WrDqDqsRunSDLLUpdWrResult while((CSR(ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n)) & 0x4) != 0x0)
| - | - | -
ampsca_ampscawrlvl_ampcawrlvlsdllcode(n) = 0x00ff02ff WrLvlMaxWrDqsSDLLCode = 0xff *read-only WrLvlRunUpdOverride = 0x0 *read-only WrLvlRunUpdWrResult = 0x0 *read-only WrLvlSDLLCode = 0xff
| - | - | -
| Poll ampscawrlvl ampcawrlvlsdllcode |
Poll: ampscawrlvl_ampcawrlvlsdllcode WrLvlRunUpdWrResult while((CSR(ampsca_ampscawrlvl_ampcawrlvlsdllcode(n)) & 0x200) != 0x0)
| - | - | -
| Program DLL Init and Incr lock timers based on 24 MHz value FPGA: Skip this step |
ampsca_ampscadllctl_dlllocktim(n) = 0x012c012c DllIncLockTim = 0x12c DllInitLockTim = 0x12c
| - | - | -
| Program DLL Init and Incr lock timers based on 24 MHz value FPGA: Skip this step |
ampsdq_ampsdqdllctl_dlllocktim(n) = 0x012c012c DllIncLockTim = 0x12c DllInitLockTim = 0x12c
| - | - | -
ampsca_ampscaRdWrDqCal_DFICalTiming(n) = 0x04000410 tCA2CAEntry = 0x10 tCA2CAExit = 0x0 tCKEHEntry = 0x4 tCKEHExit = 0x4
| - | - | -
ampsca_DFICalTiming2_DFICalTiming_f1(n) = 0x04000410 tCA2CAEntry_f1 = 0x10 tCA2CAExit_f1 = 0x0 tCKEHEntry_f1 = 0x4 tCKEHExit_f1 = 0x4
| - | - | -
ampsca_DFICalTiming2_DFICalTiming_f2(n) = 0x04000410 tCA2CAEntry_f2 = 0x10 tCA2CAExit_f2 = 0x0 tCKEHEntry_f2 = 0x4 tCKEHExit_f2 = 0x4
| - | - | -
ampsca_DFICalTiming2_DFICalTiming_f3(n) = 0x04000410 tCA2CAEntry_f3 = 0x10 tCA2CAExit_f3 = 0x0 tCKEHEntry_f3 = 0x4 tCKEHExit_f3 = 0x4
| - | - | -
ampsdq_DFICalTiming_DFICalTiming_f0(n) = 0x04020402 tCA2CAEntry_f0 = 0x2 tCA2CAExit_f0 = 0x2 tCKEHEntry_f0 = 0x4 tCKEHExit_f0 = 0x4
| - | - | -
ampsdq_DFICalTiming_DFICalTiming_f1(n) = 0x04020402 tCA2CAEntry_f1 = 0x2 tCA2CAExit_f1 = 0x2 tCKEHEntry_f1 = 0x4 tCKEHExit_f1 = 0x4
| - | - | -
ampsdq_DFICalTiming_DFICalTiming_f2(n) = 0x04020402 tCA2CAEntry_f2 = 0x2 tCA2CAExit_f2 = 0x2 tCKEHEntry_f2 = 0x4 tCKEHExit_f2 = 0x4
| - | - | -
ampsdq_DFICalTiming_DFICalTiming_f3(n) = 0x04020402 tCA2CAEntry_f3 = 0x2 tCA2CAExit_f3 = 0x2 tCKEHEntry_f3 = 0x4 tCKEHExit_f3 = 0x4
| - | - | -
ampsdq_ampsdqdllctl_MDLLCodeCaptureControl(n) = 0x00000002 MDLLLoopCnt = 0x2
| - | - | -
ampsca_ampscaRdWrDqCal_RdWrDqCalTiming_f0(n) = 0x00001426 CoarseStepSize = 0x4 *read-only FineStepSize = 0x1 tRL = 0x6 tWL = 0x2
| - | - | -
ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f0(n) = 0x00010002 tRdDqCalSegLen = 0x2 tWrDqCalSegLen = 0x1
| - | - | -
ampsca_ampscaRdWrDqCal_RdWrDqCalTiming_f1(n) = 0x00001422 CoarseStepSize = 0x4 *read-only FineStepSize = 0x1 tRL = 0x2 tWL = 0x2
| - | - | -
ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f1(n) = 0x00010002 tRdDqCalSegLen = 0x2 tWrDqCalSegLen = 0x1
| - | - | -
ampsca_ampscaRdWrDqCal_HWRdWrDqCalTimingCtrl1(n) = 0x0000301e tRd2SDLL = 0x0 tSDLL2Rd = 0x1e tSDLL2Wr = 0x30 tWr2SDLL = 0x0
| - | - | -
ampsca_ampscaRdWrDqCal_HWRdWrDqCalTimingCtrl2(n) = 0x03111004 tRd2Rd = 0x4 tRd2Wr = 0x10 tWr2Rd = 0x11 tWr2Wr = 0x3 *read-only
| - | - | -
ampsca_ampscaRdWrDqCal_HWRdDqCalPatPRBS4I(n) = 0x55555e26 PatInvertMask = 0x5555 PatPRBS4 = 0x5e26
| - | - | -
ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS4I(n) = 0x55555e26 PatInvertMask = 0x5555 PatPRBS4 = 0x5e26
| - | - | -
ampsca_ampscaRdWrDqCal_RdDqCalWindow_f0(n) = 0x00b101d1 EndPoint = 0xb1 StartPoint = 0x1d1
| - | - | -
ampsca_ampscaRdWrDqCal_WrDqCalWindow_f0(n) = 0x012f0360 EndPoint = 0x12f StartPoint = 0x360 *read-only
| - | - | -
ampsca_ampscaRdWrDqCal_RdDqCalWindow_f1(n) = 0x00f801d1 EndPoint = 0xf8 StartPoint = 0x1d1
| - | - | -
ampsca_ampscaRdWrDqCal_WrDqCalWindow_f1(n) = 0x012f0360 EndPoint = 0x12f StartPoint = 0x360 *read-only
| - | - | -
ampsca_ampscaRdWrDqCal_MaxRdDqsSDLLMulFactor(n) = 0x00a01414 MaxRdDqsSDLLCodeStatus = 0xa0 *read-only RdDqsSDLLMulFactorF0 = 0x14 RdDqsSDLLMulFactorF1 = 0x14
| - | - | -
ampsca_ampscaRdWrDqCal_MaxWrDqSDLLMulFactor(n) = 0x00a00a0f MaxWrDqSDLLCodeStatus = 0xa0 *read-only WrDqSDLLMulFactorF0 = 0xf WrDqSDLLMulFactorF1 = 0xa
| - | - | -
ampsca_ampscaRdWrDqCal_MaxWrDqsSDLLMulFactor(n) = 0xa0a00c0c MaxWrDqsSDLLCodeStatusF0 = 0xa0 *read-only MaxWrDqsSDLLCodeStatusF1 = 0xa0 *read-only WrDqsSDLLMulFactorF0 = 0xc WrDqsSDLLMulFactorF1 = 0xc
| - | - | -
ampsdq_ampsdqMulFactor_RdDqsMulFactor(n) = 0x20181000 Factor0 = 0x0 *read-only Factor1 = 0x10 Factor2 = 0x18 Factor3 = 0x20
| - | - | -
| Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) |
ampsca_ampscadllctl_caoutdllscl_freq0(n) = 0x00000008 CaOutDllScl_f0 = 0x8
| - | - | -
| Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) |
ampsdq_ampsdqdllctl_dqsindll0scl_freq0(n) = 0x00000008 DqsInDll0Scl_f0 = 0x8
| - | - | -
| Program capture latency and recapture latency |
if (platform == PALLADIUM)
ampsdq_ampsdqrdtim_rdcapcfg_freq0(n) = 0x0100080a DqIeDeAssertPullIn_f0 = 0x0 DqsPdEn_f0 = 0x1 *read-only RdCapLat_f0 = 0xa RdDatLat_f0 = 0x8 WrPhaseDelay_f0 = 0x0
else if (platform == FPGA)
ampsdq_ampsdqrdtim_rdcapcfg_freq0(n) = 0x01000606 DqIeDeAssertPullIn_f0 = 0x0 DqsPdEn_f0 = 0x1 *read-only RdCapLat_f0 = 0x6 RdDatLat_f0 = 0x6 WrPhaseDelay_f0 = 0x0
else
ampsdq_ampsdqrdtim_rdcapcfg_freq0(n) = 0x0100080d DqIeDeAssertPullIn_f0 = 0x0 DqsPdEn_f0 = 0x1 *read-only RdCapLat_f0 = 0xd RdDatLat_f0 = 0x8 WrPhaseDelay_f0 = 0x0
| - | - | -
| Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) |
ampsca_ampscadllctl_caoutdllscl_freq1(n) = 0x0000000c CaOutDllScl_f1 = 0xc
| - | - | -
| Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) |
ampsdq_ampsdqdllctl_dqsindll0scl_freq1(n) = 0x0000000c DqsInDll0Scl_f1 = 0xc
| - | - | -
| Program capture latency and recapture latency |
if (platform == FPGA)
ampsdq_ampsdqrdtim_rdcapcfg_freq1(n) = 0x21000606 DqIeDeAssertPullIn_f1 = 0x2 DqsPdEn_f1 = 0x1 *read-only RdCapLat_f1 = 0x6 RdDatLat_f1 = 0x6 WrPhaseDelay_f1 = 0x0
else
ampsdq_ampsdqrdtim_rdcapcfg_freq1(n) = 0x2100070a DqIeDeAssertPullIn_f1 = 0x2 DqsPdEn_f1 = 0x1 *read-only RdCapLat_f1 = 0xa RdDatLat_f1 = 0x7 WrPhaseDelay_f1 = 0x0
| - | - | -
| Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) |
ampsca_ampscadllctl_caoutdllscl_freq2(n) = 0x00000030 CaOutDllScl_f2 = 0x30
| - | - | -
| Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) |
ampsdq_ampsdqdllctl_dqsindll0scl_freq2(n) = 0x00000030 DqsInDll0Scl_f2 = 0x30
| - | - | -
| Program capture latency and recapture latency |
if (platform == PALLADIUM)
ampsdq_ampsdqrdtim_rdcapcfg_freq2(n) = 0x4100050a DqIeDeAssertPullIn_f2 = 0x4 DqsPdEn_f2 = 0x1 *read-only RdCapLat_f2 = 0xa RdDatLat_f2 = 0x5 WrPhaseDelay_f2 = 0x0
else if (platform == FPGA)
ampsdq_ampsdqrdtim_rdcapcfg_freq2(n) = 0x41000606 DqIeDeAssertPullIn_f2 = 0x4 DqsPdEn_f2 = 0x1 *read-only RdCapLat_f2 = 0x6 RdDatLat_f2 = 0x6 WrPhaseDelay_f2 = 0x0
else
ampsdq_ampsdqrdtim_rdcapcfg_freq2(n) = 0x41000508 DqIeDeAssertPullIn_f2 = 0x4 DqsPdEn_f2 = 0x1 *read-only RdCapLat_f2 = 0x8 RdDatLat_f2 = 0x5 WrPhaseDelay_f2 = 0x0
| - | - | -
| Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) |
ampsca_ampscadllctl_caoutdllscl_freq3(n) = 0x0000003f CaOutDllScl_f3 = 0x3f
| - | - | -
| Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) |
ampsdq_ampsdqdllctl_dqsindll0scl_freq3(n) = 0x0000003f DqsInDll0Scl_f3 = 0x3f
| - | - | -
| Program capture latency and recapture latency |
if (platform == PALLADIUM)
ampsdq_ampsdqrdtim_rdcapcfg_freq3(n) = 0x6100050a DqIeDeAssertPullIn_f3 = 0x6 DqsPdEn_f3 = 0x1 *read-only RdCapLat_f3 = 0xa RdDatLat_f3 = 0x5 WrPhaseDelay_f3 = 0x0
else if (platform == FPGA)
ampsdq_ampsdqrdtim_rdcapcfg_freq3(n) = 0x61000606 DqIeDeAssertPullIn_f3 = 0x6 DqsPdEn_f3 = 0x1 *read-only RdCapLat_f3 = 0x6 RdDatLat_f3 = 0x6 WrPhaseDelay_f3 = 0x0
else
ampsdq_ampsdqrdtim_rdcapcfg_freq3(n) = 0x61000508 DqIeDeAssertPullIn_f3 = 0x6 DqsPdEn_f3 = 0x1 *read-only RdCapLat_f3 = 0x8 RdDatLat_f3 = 0x5 WrPhaseDelay_f3 = 0x0
| - | - | -
| Updating the programming of DLL*UpdtDur Fields FPGA: Skip this step |
ampsca_ampscadllctl_dllupdtctrl(n) = 0x50017550 DllInitUpdtDur = 0x7 DllUpdtDur = 0x5 DllUpdtMode = 0x1 DllUpdtPhyUpdtTyp = 0x0 *read-only FreqChangeSDLLUpdDur = 0x50 *read-only SDLLUpdDur = 0x50 *read-only
| - | - | -
| Updating the programming of DLL*UpdtDur Fields FPGA: Skip this step |
ampsdq_ampsdqdllctl_dllupdtctrl(n) = 0x50017550 DllInitUpdtDur = 0x7 DllUpdtDur = 0x5 DllUpdtMode = 0x1 DllUpdtPhyUpdtTyp = 0x0 *read-only FreqChangeSDLLUpdDur = 0x50 *read-only SDLLUpdDur = 0x50 *read-only
| - | - | -
| FPGA: Skip this step |
ampsca_ampscaiocfg_impautocal(n) = 0x00010000 impautocalen = 0x1 impcalintvl = 0x0 *read-only impcaltype = 0x0
| - | - | -
ampsca_ampscadllctl_dllupdtintvl(n) = 0x10200020 DllFastUpdtAlwaysON = 0x1 *read-only DllFastUpdtIntvl = 0x20 *read-only DllUpdtAlwaysON = 0x0 DllUpdtIntvl = 0x20 *read-only
| - | - | -
ampsdq_ampsdqdllctl_dllupdtintvl(n) = 0x10200020 DllFastUpdtAlwaysON = 0x1 *read-only DllFastUpdtIntvl = 0x20 *read-only DllUpdtAlwaysON = 0x0 DllUpdtIntvl = 0x20 *read-only
| - | - | -
| Enable DLL |
ampsca_ampscadllctl_dllen(n) = 0x00000100 DLLEn = 0x1 MDllReset = 0x0 *read-only
| - | - | -
| Enable DLL |
ampsdq_ampsdqdllctl_dllen(n) = 0x00000100 DLLEn = 0x1 MDllReset = 0x0 *read-only
| - | - | -
| Run impedance calibration and optionally enable periodic auto impedance calibration FPGA: Skip this step |
ampsca_ampscaiocfg_impcalcmd(n) = 0x00000000 RunImpCal = 0x0 *read-only RunImpCalType = 0x0
| - | - | -
amph_CFGH_CB_WKPUPD(n) = 0x00000000 pdpwk_f0 = 0x0 *read-only pdpwk_f1 = 0x0 *read-only pdpwk_f2 = 0x0 *read-only pdpwk_f3 = 0x0 *read-only pupwk_f0 = 0x0 *read-only pupwk_f1 = 0x0 *read-only pupwk_f2 = 0x0 *read-only pupwk_f3 = 0x0 *read-only wkds = 0x0
| - | - | -
amph_CFGH_CB_DRIVE_STR(n) = 0x33831717 dspd_f0 = 0x7 dspd_f1 = 0x7 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x1 dspu_f2 = 0x8 dspu_f3 = 0x3
| - | - | -
amph_CFGH_CB_IOCTL(n) = 0x000200a3 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x0 *read-only en_pulse_tx_f3 = 0x0 isel = 0x0 protect_drvstren = 0x1 *read-only sel_rx_ac = 0x0 *read-only sel_rx_dc = 0x0 *read-only tx_ac_f0 = 0x2 tx_ac_f1 = 0x2 tx_ac_f2 = 0x0 *read-only tx_ac_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_CK_WKPUPD(n) = 0x00000000 pdpwk_f0 = 0x0 *read-only pdpwk_f1 = 0x0 *read-only pdpwk_f2 = 0x0 *read-only pdpwk_f3 = 0x0 *read-only pupwk_f0 = 0x0 *read-only pupwk_f1 = 0x0 *read-only pupwk_f2 = 0x0 *read-only pupwk_f3 = 0x0 *read-only wkds = 0x0
| - | - | -
amph_CFGH_CK_ZDET_BIASEN(n) = 0x00000000 bias_ena = 0x0 *read-only disable_zdet = 0x0 sel_zdet = 0x0 *read-only
| - | - | -
amph_CFGH_CK_DRIVE_STR(n) = 0x33831717 dspd_f0 = 0x7 dspd_f1 = 0x7 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x1 dspu_f2 = 0x8 dspu_f3 = 0x3
| - | - | -
amph_CFGH_CK_IOCTL(n) = 0x000000a7 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x1 en_pulse_tx_f3 = 0x0 isel = 0x0 sel_rx_ac = 0x0 *read-only sel_rx_dc = 0x0 *read-only tx_ac_f0 = 0x2 tx_ac_f1 = 0x2 tx_ac_f2 = 0x0 *read-only tx_ac_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_B0_DRIVE_STR(n) = 0x33831717 dspd_f0 = 0x7 dspd_f1 = 0x7 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x1 dspu_f2 = 0x8 dspu_f3 = 0x3
| - | - | -
amph_CFGH_B0_IMPCTL(n) = 0x00201c2b en160_tx_f0 = 0x0 en160_tx_f1 = 0x1 en160_tx_f2 = 0x0 en160_tx_f3 = 0x0 zcpd_ovrr = 0x1c *read-only zcpu_ovrr = 0x2b *read-only zcpu_pd_ovrr = 0x0 *read-only
| - | - | -
amph_CFGH_B0_WKPUPD(n) = 0x00000000 idle_active_en_f0 = 0x0 *read-only idle_active_en_f1 = 0x0 *read-only idle_active_en_f2 = 0x0 *read-only idle_active_en_f3 = 0x0 *read-only pdpwk_f0 = 0x0 pdpwk_f1 = 0x0 pdpwk_f2 = 0x0 pdpwk_f3 = 0x0 pupwk_f0 = 0x0 pupwk_f1 = 0x0 pupwk_f2 = 0x0 pupwk_f3 = 0x0 wkds = 0x0
| - | - | -
amph_CFGH_B0_IOCTL(n) = 0x715000a7 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x1 en_pulse_tx_f3 = 0x0 isel_f0 = 0x1 isel_f1 = 0x1 isel_f2 = 0x1 isel_f3 = 0x0 sel_rx_ac_f0 = 0x0 sel_rx_ac_f1 = 0x0 sel_rx_ac_f2 = 0x0 sel_rx_ac_f3 = 0x0 sel_rx_dc_f0 = 0x1 sel_rx_dc_f1 = 0x1 sel_rx_dc_f2 = 0x1 sel_rx_dc_f3 = 0x0 tx_ac_f0 = 0x2 tx_ac_f1 = 0x2 tx_ac_f2 = 0x0 *read-only tx_ac_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_B0_ODT(n) = 0x01c00333 dspd_f0 = 0x3 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x0 zcpd_ovrr = 0x0 *read-only zcpd_val = 0x1c *read-only
| - | - | -
if (platform == PALLADIUM)
amph_CFGH_B0_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else if (platform == FPGA)
amph_CFGH_B0_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else
amph_CFGH_B0_ODTCTRL(n) = 0x00000005 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x1 *read-only odten_f1 = 0x0 odten_f2 = 0x1 *read-only odten_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_B1_DRIVE_STR(n) = 0x33831717 dspd_f0 = 0x7 dspd_f1 = 0x7 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x1 dspu_f2 = 0x8 dspu_f3 = 0x3
| - | - | -
if (platform == PALLADIUM)
amph_CFGH_B1_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else if (platform == FPGA)
amph_CFGH_B1_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else
amph_CFGH_B1_ODTCTRL(n) = 0x00000005 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x1 *read-only odten_f1 = 0x0 odten_f2 = 0x1 *read-only odten_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_B1_IMPCTL(n) = 0x00201c2b en160_tx_f0 = 0x0 en160_tx_f1 = 0x1 en160_tx_f2 = 0x0 en160_tx_f3 = 0x0 zcpd_ovrr = 0x1c *read-only zcpu_ovrr = 0x2b *read-only zcpu_pd_ovrr = 0x0 *read-only
| - | - | -
amph_CFGH_B1_WKPUPD(n) = 0x00000000 idle_active_en_f0 = 0x0 *read-only idle_active_en_f1 = 0x0 *read-only idle_active_en_f2 = 0x0 *read-only idle_active_en_f3 = 0x0 *read-only pdpwk_f0 = 0x0 pdpwk_f1 = 0x0 pdpwk_f2 = 0x0 pdpwk_f3 = 0x0 pupwk_f0 = 0x0 pupwk_f1 = 0x0 pupwk_f2 = 0x0 pupwk_f3 = 0x0 wkds = 0x0
| - | - | -
amph_CFGH_B1_IOCTL(n) = 0x715000a7 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x1 en_pulse_tx_f3 = 0x0 isel_f0 = 0x1 isel_f1 = 0x1 isel_f2 = 0x1 isel_f3 = 0x0 sel_rx_ac_f0 = 0x0 sel_rx_ac_f1 = 0x0 sel_rx_ac_f2 = 0x0 sel_rx_ac_f3 = 0x0 sel_rx_dc_f0 = 0x1 sel_rx_dc_f1 = 0x1 sel_rx_dc_f2 = 0x1 sel_rx_dc_f3 = 0x0 tx_ac_f0 = 0x2 tx_ac_f1 = 0x2 tx_ac_f2 = 0x0 *read-only tx_ac_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_B1_ODT(n) = 0x01c00333 dspd_f0 = 0x3 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x0 zcpd_ovrr = 0x0 *read-only zcpd_val = 0x1c *read-only
| - | - | -
amph_CFGH_DQS0_WKPUPD(n) = 0x00000788 idle_active_en_f0 = 0x0 *read-only idle_active_en_f1 = 0x0 *read-only idle_active_en_f2 = 0x0 *read-only idle_active_en_f3 = 0x0 *read-only pdpwk_f0 = 0x0 *read-only pdpwk_f1 = 0x1 pdpwk_f2 = 0x0 *read-only pdpwk_f3 = 0x1 *read-only pupwk_f0 = 0x0 *read-only pupwk_f1 = 0x0 *read-only pupwk_f2 = 0x0 *read-only pupwk_f3 = 0x0 *read-only wkds = 0x7 *read-only
| - | - | -
amph_CFGH_DQS0_DRIVE_STR(n) = 0x33831717 dspd_f0 = 0x7 dspd_f1 = 0x7 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x1 dspu_f2 = 0x8 dspu_f3 = 0x3
| - | - | -
amph_CFGH_DQS0_IMPCTL(n) = 0x00201c2b en160_tx_f0 = 0x0 en160_tx_f1 = 0x1 en160_tx_f2 = 0x0 en160_tx_f3 = 0x0 zcpd_ovrr = 0x1c *read-only zcpu_ovrr = 0x2b *read-only zcpu_pd_ovrr = 0x0 *read-only
| - | - | -
amph_CFGH_DQS0_IOCTL(n) = 0x715000a7 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x1 en_pulse_tx_f3 = 0x0 isel_f0 = 0x1 isel_f1 = 0x1 isel_f2 = 0x1 isel_f3 = 0x0 sel_rx_ac_f0 = 0x0 sel_rx_ac_f1 = 0x0 sel_rx_ac_f2 = 0x0 sel_rx_ac_f3 = 0x0 sel_rx_dc_f0 = 0x1 sel_rx_dc_f1 = 0x1 sel_rx_dc_f2 = 0x1 sel_rx_dc_f3 = 0x0 tx_ac_f0 = 0x2 tx_ac_f1 = 0x2 tx_ac_f2 = 0x0 *read-only tx_ac_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_DQS0_ODT(n) = 0x01c00333 dspd_f0 = 0x3 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x0 zcpd_ovrr = 0x0 *read-only zcpd_val = 0x1c *read-only
| - | - | -
amph_CFGH_DQS0_ZDET_BIASEN(n) = 0x00060028 bias_ena_f0 = 0x0 bias_ena_f1 = 0x1 bias_ena_f2 = 0x1 bias_ena_f3 = 0x0 disable_zdet_f0 = 0x0 disable_zdet_f1 = 0x0 disable_zdet_f2 = 0x0 disable_zdet_f3 = 0x0 sel_zdet_f0 = 0x0 sel_zdet_f1 = 0x2 sel_zdet_f2 = 0x2 sel_zdet_f3 = 0x0
| - | - | -
if (platform == PALLADIUM)
amph_CFGH_DQS0_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else if (platform == FPGA)
amph_CFGH_DQS0_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else
amph_CFGH_DQS0_ODTCTRL(n) = 0x00000007 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x1 *read-only odten_f1 = 0x1 odten_f2 = 0x1 *read-only odten_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_DQS1_WKPUPD(n) = 0x00000788 idle_active_en_f0 = 0x0 *read-only idle_active_en_f1 = 0x0 *read-only idle_active_en_f2 = 0x0 *read-only idle_active_en_f3 = 0x0 *read-only pdpwk_f0 = 0x0 *read-only pdpwk_f1 = 0x1 pdpwk_f2 = 0x0 *read-only pdpwk_f3 = 0x1 *read-only pupwk_f0 = 0x0 *read-only pupwk_f1 = 0x0 *read-only pupwk_f2 = 0x0 *read-only pupwk_f3 = 0x0 *read-only wkds = 0x7 *read-only
| - | - | -
amph_CFGH_DQS1_DRIVE_STR(n) = 0x33831717 dspd_f0 = 0x7 dspd_f1 = 0x7 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x1 dspu_f2 = 0x8 dspu_f3 = 0x3
| - | - | -
amph_CFGH_DQS1_IMPCTL(n) = 0x00201c2b en160_tx_f0 = 0x0 en160_tx_f1 = 0x1 en160_tx_f2 = 0x0 en160_tx_f3 = 0x0 zcpd_ovrr = 0x1c *read-only zcpu_ovrr = 0x2b *read-only zcpu_pd_ovrr = 0x0 *read-only
| - | - | -
amph_CFGH_DQS1_IOCTL(n) = 0x715000a7 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x1 en_pulse_tx_f3 = 0x0 isel_f0 = 0x1 isel_f1 = 0x1 isel_f2 = 0x1 isel_f3 = 0x0 sel_rx_ac_f0 = 0x0 sel_rx_ac_f1 = 0x0 sel_rx_ac_f2 = 0x0 sel_rx_ac_f3 = 0x0 sel_rx_dc_f0 = 0x1 sel_rx_dc_f1 = 0x1 sel_rx_dc_f2 = 0x1 sel_rx_dc_f3 = 0x0 tx_ac_f0 = 0x2 tx_ac_f1 = 0x2 tx_ac_f2 = 0x0 *read-only tx_ac_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_DQS1_ODT(n) = 0x01c00333 dspd_f0 = 0x3 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x0 zcpd_ovrr = 0x0 *read-only zcpd_val = 0x1c *read-only
| - | - | -
amph_CFGH_DQS1_ZDET_BIASEN(n) = 0x00060028 bias_ena_f0 = 0x0 bias_ena_f1 = 0x1 bias_ena_f2 = 0x1 bias_ena_f3 = 0x0 disable_zdet_f0 = 0x0 disable_zdet_f1 = 0x0 disable_zdet_f2 = 0x0 disable_zdet_f3 = 0x0 sel_zdet_f0 = 0x0 sel_zdet_f1 = 0x2 sel_zdet_f2 = 0x2 sel_zdet_f3 = 0x0
| - | - | -
if (platform == PALLADIUM)
amph_CFGH_DQS1_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else if (platform == FPGA)
amph_CFGH_DQS1_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else
amph_CFGH_DQS1_ODTCTRL(n) = 0x00000007 dspu_f0 = 0x0 *read-only dspu_f1 = 0x0 *read-only dspu_f2 = 0x0 *read-only dspu_f3 = 0x0 *read-only odten_f0 = 0x1 *read-only odten_f1 = 0x1 odten_f2 = 0x1 *read-only odten_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_DBG_DBG_REG0(n) = 0x00000000 cb_bias_ena = 0x0 cb_odte = 0x0 *read-only clk_en_sync_flop_rst = 0x0 *read-only mon_vdd_mem = 0x0 *read-only mon_vdd_soc = 0x0 *read-only
| - | - | -
amph_CFGH_ZC_ZCAL_FSM1(n) = 0x00667f7f bias_ena_dly = 0x66 io_pd = 0x7f *read-only io_pu = 0x7f *read-only
| - | - | -
amph_CFGH_ZC_ZCAL_FSM0(n) = 0x000f0315 zc_dly = 0x15 zc_dnbd = 0x0 zc_tap = 0x3 zc_upbd = 0xf
| - | - | -
amph_CFGH_DEBUG_SPARE0(n) = 0x0000000e control = 0xe
| - | - | -
| Assert init_done |
ampsca_ampscagen_ampinit(n) = 0x00000001 InitDone = 0x1
| - | - | -
| Assert init_done |
ampsdq_ampsdqgen_ampinit(n) = 0x00000001 InitDone = 0x1
| - | - | -

#### 3. Self-Refresh Exit

Prior to this step, the DRAM is assumed to be in the self-refresh state, and CKE has been kept low, either by retention circuitry in the PHY/IO, or, after SOC power is up and the reset is done, by the controller. This step will take DRAM out of the self-refresh mode. Software must guarantee that at least 50 us have passed since the de- assertion of AMC reset before self-refresh exit, in the resume-boot case. The frequency change to 50MHz here is initiated by PMGR. For ResumeBoot, the auto-refresh must be enabled before exiting self-refresh state.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| Wait 5us after Impedance Calibration in Step2. This is to avoid McPhyPending preventing the SRFSM from exiting SR. |  | - | - | -
| radar #8707478 has been fixed. SetSRExitRefCnt to 2. |
amcx_dramcfg_arefparam(n) = 0x08010019 FreqChngWaitThr = 0x1 PhyUpdWaitRefresh = 0x1 PhyUpdWaitThr = 0x1 *read-only PhyUpdWaittXSR = 0x0 RefAssertCnt = 0x8 SRExitRefCnt = 0x1
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_autoref_freq3(n) = 0x24480050 tRFCBaseCyc_freq3 = 0x50 tRFCCyc_freq3 = 0x48 tRFCpbCyc_freq3 = 0x24
else if (platform == FPGA)
amcx_dramtim_autoref_freq3(n) = 0x01010001 tRFCBaseCyc_freq3 = 0x1 tRFCCyc_freq3 = 0x1 tRFCpbCyc_freq3 = 0x1
else
amcx_dramtim_autoref_freq3(n) = 0x03050005 tRFCBaseCyc_freq3 = 0x5 tRFCCyc_freq3 = 0x5 tRFCpbCyc_freq3 = 0x3
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_autoref_freq2(n) = 0x24480050 tRFCBaseCyc_freq2 = 0x50 tRFCCyc_freq2 = 0x48 tRFCpbCyc_freq2 = 0x24
else if (platform == FPGA)
amcx_dramtim_autoref_freq2(n) = 0x01010001 tRFCBaseCyc_freq2 = 0x1 tRFCCyc_freq2 = 0x1 tRFCpbCyc_freq2 = 0x1
else
amcx_dramtim_autoref_freq2(n) = 0x09120013 tRFCBaseCyc_freq2 = 0x13 tRFCCyc_freq2 = 0x12 tRFCpbCyc_freq2 = 0x9
| - | - | -
| **IMPORTANT** : For power saving on SOC's using Samsung and Hynix DRAM's, it's mandatory to set autoref_freq1 to 0x1C480049. For SOC's using Micron DRAM, autoref_freq1 should be set to 0x20480049.
if (platform == FPGA)
amcx_dramtim_autoref_freq1(n) = 0x01010001 tRFCBaseCyc_freq1 = 0x1 tRFCCyc_freq1 = 0x1 tRFCpbCyc_freq1 = 0x1
else
amcx_dramtim_autoref_freq1(n) = 0x24480049 tRFCBaseCyc_freq1 = 0x49 tRFCCyc_freq1 = 0x48 tRFCpbCyc_freq1 = 0x24
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_autoref_freq0(n) = 0x24480050 tRFCBaseCyc_freq0 = 0x50 tRFCCyc_freq0 = 0x48 tRFCpbCyc_freq0 = 0x24
else if (platform == FPGA)
amcx_dramtim_autoref_freq0(n) = 0x01010001 tRFCBaseCyc_freq0 = 0x1 tRFCCyc_freq0 = 0x1 tRFCpbCyc_freq0 = 0x1
else
amcx_dramtim_autoref_freq0(n) = 0x366c006e tRFCBaseCyc_freq0 = 0x6e tRFCCyc_freq0 = 0x6c tRFCpbCyc_freq0 = 0x36
| - | - | -
if (platform == PALLADIUM)
amcx_dramtim_autoref_params(n) = 0x0017005d tREFBWtRFCcnt = 0x17 tREFICyc = 0x5d
else if (platform == FPGA)
amcx_dramtim_autoref_params(n) = 0x00170013 tREFBWtRFCcnt = 0x17 tREFICyc = 0x13
else
amcx_dramtim_autoref_params(n) = 0x0017005d tREFBWtRFCcnt = 0x17 tREFICyc = 0x5d
| - | - | -
| Enable auto refresh derating by setting TempDrtEn to 1. However, we do not enable ODTS interval until the end of the init. Setting TempDrtEn to 1 allows the chip to be in the hi-temp state and become more conservative. |
if (platform == FPGA)
amcx_dramcfg_odtszqc(n) = 0x00000000 DerateParamSRExit = 0x0 OdtsRdIntrvl = 0x0 SRExitZQCChnlQuiet = 0x0 *read-only ShareZQRes = 0x0 *read-only TempDrtEn = 0x0 ZQCChnlQuiet = 0x0 *read-only ZQCStack = 0x0 *read-only ZqCalIntrvl = 0x0 *read-only
else
amcx_dramcfg_odtszqc(n) = 0x00001000 DerateParamSRExit = 0x0 OdtsRdIntrvl = 0x0 SRExitZQCChnlQuiet = 0x0 *read-only ShareZQRes = 0x0 *read-only TempDrtEn = 0x1 ZQCChnlQuiet = 0x0 *read-only ZQCStack = 0x0 *read-only ZqCalIntrvl = 0x0 *read-only
| - | - | -
| set SRExtraRefCnt to correct value (which is 1) and set LongSRCnt to be tREFW/4 (32ms/4=8ms) If RefCntrHiWaterMark is changed from its default value, then LongSRExitRefCnt needs to be programmed to the same value. Palladium: LongSRCnt=0x1004 because Palladium uses 1Gb device. |
amcx_dramcfg_longsr(n) = 0x01012008 LongSRCnt = 0x2008 LongSRExitRefCnt = 0x1 SRExtraRefCnt = 0x1
| - | - | -
amcx_dramcfg_mcphyupdtparam(n) = 0x15030007 FreqCSettleCyc = 0x5 *read-only McPhyTimeParamCyc = 0x3 PhyInitStartCyc = 0x0 PhyUpdMDLL = 0x1 UpdPhyLatCyc = 0x0 *read-only tPhyUpdGap = 0x7
| - | - | -
| Call custom API provided by PMGR for changing mcu_clk to 55Mhz and mcu_fixed_clk to Mhz // TO BE COMPLETED FPGA: Skip this step |  | - | - | -
| Wait 5us to avoid a race condition between frequency change to bucket 3 & MCU being enabled |  | - | - | -
| Turn on enables for various AMC blocks MCU. |
amcx_amcgen_amcctrl(n) = 0x00000003 McuEn = 0x1 SchEn = 0x1
| - | - | -
| Run impedance calibration and optionally enable periodic auto impedance calibration FPGA: Skip this step |
ampsca_ampscaiocfg_impcalcmd(n) = 0x00000001 RunImpCal = 0x0 *read-only RunImpCalType = 0x0
| - | - | -
| Poll ampscaiocfg impcalcmd FPGA: Skip this step |
Poll: ampscaiocfg_impcalcmd RunImpCal while((CSR(ampsca_ampscaiocfg_impcalcmd(n)) & 0x1) != 0x0)
| - | - | -
amcx_dramcfg_arefen_freq3(n) = 0x11100000 ARpbEn_freq3 = 0x0 HiTempRefRnkAgeOut_freq3 = 0x1 RefCntrHiWaterMark_freq3 = 0x1 RefCntrLoWaterMark_freq3 = 0x1
| - | Yes | -
amcx_dramcfg_arefen_freq2(n) = 0x11000000 ARpbEn_freq2 = 0x0 HiTempRefRnkAgeOut_freq2 = 0x0 RefCntrHiWaterMark_freq2 = 0x1 RefCntrLoWaterMark_freq2 = 0x1
| - | Yes | -
amcx_dramcfg_arefen_freq1(n) = 0x11110000 ARpbEn_freq1 = 0x1 *read-only HiTempRefRnkAgeOut_freq1 = 0x1 RefCntrHiWaterMark_freq1 = 0x1 RefCntrLoWaterMark_freq1 = 0x1
| - | Yes | -
| Turn on auto refresh. |
amcx_dramcfg_arefen_freq0(n) = 0x1111013f ARpbEn_freq0 = 0x1 AutoRefEn = 0x1 AutoRefSchEn = 0x1 DisableHiTempREFab = 0x1 EarlyCasAgeOut = 0x0 HiPriREFpbPch = 0x1 HiTempRefRnkAgeOut_freq0 = 0x1 REFpb2bank = 0x0 REFpbEarlyPch = 0x1 RefCntrHiWaterMark_freq0 = 0x1 RefCntrLoWaterMark_freq0 = 0x1 RefOpptEn = 0x1 tREFBWREFpb = 0x1
| - | Yes | -
| Wait 200us for tINIT1 in real init, which we have cooked down to 200ns for simulation. |  | - | - | -
| Wait 2 ms for tINIT3 in real init, which we have cooked down to 200ns for simulation. |  | - | - | -
amcx_dramcfg_freqchngctl(n) = 0x00010000 freqchngfspop = 0x0 *read-only freqchngmrwcnt_freq0 = 0x0 *read-only freqchngmrwcnt_freq1 = 0x0 *read-only freqchngmrwcnt_freq2 = 0x0 *read-only freqchngmrwcnt_freq3 = 0x0 *read-only freqchngrunsocupd = 0x0 *read-only
| - | - | -
| Poll dramcfg freqchngctl |
Poll: dramcfg_freqchngctl freqchngrunsocupd while((CSR(amcx_dramcfg_freqchngctl(n)) & 0x10000) != 0x0)
| - | - | -
amcx_dramcfg_freqchngctl(n) = 0x00000000 freqchngfspop = 0x0 *read-only freqchngmrwcnt_freq0 = 0x0 *read-only freqchngmrwcnt_freq1 = 0x0 *read-only freqchngmrwcnt_freq2 = 0x0 *read-only freqchngmrwcnt_freq3 = 0x0 *read-only freqchngrunsocupd = 0x0 *read-only
| - | - | -
| Wait 2us for the soc update to finish |  | - | - | -
| Assert MPC to Sending SR Exit during Resume Boot |
amcx_dramcmd_mrinitcmd(n) = 0x00004000 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | Yes | -
| Issue self-refresh exit command. One for each channel. SW needs to guarantee that at least 50usec has passed since removal of reset to AMC before issuing the self-refresh exit command, in case of resume boot. |
amcx_dramcmd_mrinitcmd(n) = 0x00004001 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | Yes | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunSRExit while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x1) != 0x0)
| - | Yes | -
| Assert MPC to Sending SR Exit during Resume Boot |
amcx_dramcmd_mrinitcmd(n) = 0x00000000 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Issue self-refresh exit command. One for each channel. SW needs to guarantee that at least 50usec has passed since removal of reset to AMC before issuing the self-refresh exit command, in case of resume boot. |
amcx_dramcmd_mrinitcmd(n) = 0x00000001 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunSRExit while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x1) != 0x0)
| - | No | -
| Wait 2 us for tINIT5 in real init, which we have cooked down to 200ns for simulation. |  | - | - | -
glbtimer_GlbTimer_ChEn = 0x0000000f ChEn = 0xf
| - | - | -

#### 4. DRAM Reset, ZQ Calibration & Configuration (Cold Boot Only).

This step is only required for ColdBoot. This step is to be repeated for each of the number of ranks per channel. The dramcmd.mrcmdch{N}.MRCmdCsCh{N} bit (Noted by letter R in the section) should be incremented in each loop.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| Issue DRAM ZQ calibration START MPC command MRINIT CMD registers. Note that the MPC command can be issued to different channels independently, as long as the system has separate ZQ reference resistor for eachchannel. TheZQcalibration MPC to each rank within the same channel must be issued in series. |
amcx_dramcmd_mrinitcmd(n) = 0x4f004100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | - | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | - | -
| Wait 1us for tZQCAL. |  | - | - | -
| Issue DRAM ZQ calibration LATCH MPC command MRINIT CMD registers |
amcx_dramcmd_mrinitcmd(n) = 0x51004100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | - | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | - | -
| Wait 20ns for tZQLAT. |  | - | - | -
| Configure DRAM MR2 register (latency) through MRR/MRW command registers. The example shows the nominal programming for LPDDR2-1066 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices. |
amcx_dramcmd_mrinitcmd(n) = 0x00020100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Configure DRAM MR1 register through MRR/MRW command registers. This includes the following: WC=Wrap BT=Sequential BL=BL16. nWR, the example shows the nominal programming for LPDDR3- 1600 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices. |
amcx_dramcmd_mrinitcmd(n) = 0x8e010100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
amcx_dramcmd_mrinitcmd(n) = 0xf3030100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
amcx_dramcmd_mrinitcmd(n) = 0x00160100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x000b0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Program MR11 for FPGA FPGA: Perform this step |
amcx_dramcmd_mrinitcmd(n) = 0x000b0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Perform this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Program VRCG and Modified Refresh to 1 |
amcx_dramcmd_mrinitcmd(n) = 0x180d0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
amcx_dramcmd_mrinitcmd(n) = 0x590c0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
amcx_dramcmd_mrinitcmd(n) = 0x590e0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
amcx_dramcmd_mrinitcmd(n) = 0x80170100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Program MR15/20 to match PatInvertMask of HW RdDQ calibration |
amcx_dramcmd_mrinitcmd(n) = 0x550f4100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Program MR15/20 to match PatInvertMask of HW RdDQ calibration |
amcx_dramcmd_mrinitcmd(n) = 0x55144100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Program MR32/40 to match the PatPRBS4 pattern for HW RdDQ calibration |
amcx_dramcmd_mrinitcmd(n) = 0x26204100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Program MR32/40 to match the PatPRBS4 pattern for HW RdDQ calibration |
amcx_dramcmd_mrinitcmd(n) = 0x5e284100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -

#### 5. Topology-specific configuration.

Here we perform MRR's to the memory to find out device density and program addrcfg, DramAccCtrl and mccchnldec registers

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
if (platform == ONE_CH_TWO_RANK)
amcc_MccLockRegion_addrcfg = 0x01030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x1 RowAddrWid = 0x3
else if (platform == TWO_CH_TWO_RANK)
amcc_MccLockRegion_addrcfg = 0x01030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x1 RowAddrWid = 0x3
else if (platform == FOUR_CH_TWO_RANK)
amcc_MccLockRegion_addrcfg = 0x01030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x1 RowAddrWid = 0x3
else
amcc_MccLockRegion_addrcfg = 0x00030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x0 RowAddrWid = 0x3
| - | - | -
if (platform == FPGA_LPDDR3)
amcc_MccLockRegion_DramAccCtrl = 0x00000007 DramSize = 0x7
else if (platform == ONE_CH_ONE_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x00000003 DramSize = 0x3
else if (platform == ONE_CH_TWO_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x00000007 DramSize = 0x7
else if (platform == FOUR_CH_ONE_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x0000000f DramSize = 0xf
else if (platform == TWO_CH_TWO_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x0000000f DramSize = 0xf
else if (platform == FPGA)
amcc_MccLockRegion_DramAccCtrl = 0x0000000f DramSize = 0xf
else if (platform == FOUR_CH_TWO_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x0000001f DramSize = 0x1f
else if (platform == TWO_CH_ONE_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x00000007 DramSize = 0x7
else
amcc_MccLockRegion_DramAccCtrl = 0x0000000f DramSize = 0xf
| - | - | -
| dram_Density_config(); |  | - | - | -
if (platform == ONE_CH_ONE_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050201 ChSelHiBits = 0x5 ChSelTyp = 0x1 ChnlStartBit = 0x2 NumMcuChnl = 0x0
else if (platform == ONE_CH_TWO_RANK)
amcc_MccLockRegion_mccchnldec = 0x00060201 ChSelHiBits = 0x6 ChSelTyp = 0x1 ChnlStartBit = 0x2 NumMcuChnl = 0x0
else if (platform == TWO_CH_TWO_RANK)
amcc_MccLockRegion_mccchnldec = 0x00060210 ChSelHiBits = 0x6 ChSelTyp = 0x0 ChnlStartBit = 0x2 NumMcuChnl = 0x1
else if (platform == FOUR_CH_TWO_RANK)
amcc_MccLockRegion_mccchnldec = 0x00060220 ChSelHiBits = 0x6 ChSelTyp = 0x0 ChnlStartBit = 0x2 NumMcuChnl = 0x2
else
amcc_MccLockRegion_mccchnldec = 0x00050220 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x2 NumMcuChnl = 0x2
| - | - | -

#### 6. Prepare for switch from boot-clock speed to normal operation speed

The frequency change is initiated by PMGR.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| Wait 5us before issuing a freq change to make sure all refreshes have been flushed. |  | - | - | -
| Enable AMC scheduler to allow normal transactions to be processed. Scheduler has to be enabled to let AMC issue self-refresh entry and allow frequency change. |
amcx_amcgen_amcctrl(n) = 0x00000003 McuEn = 0x1 SchEn = 0x1
| - | - | -

#### 7. Setup registers for CA calibration for bucket 1

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| Program FSP-WR to 1, and set VRCG and modified refresh FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x580d0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Configure DRAM MR2 register (latency) through MRR/MRW command registers. The example shows the nominal programming for LPDDR2-1066 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices. FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x52020100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Configure DRAM MR1 register through MRR/MRW command registers. This includes the following: WC=Wrap BT=Sequential BL=BL16. nWR, the example shows the nominal programming for LPDDR3- 1600 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices. FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0xae010100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0xf3030100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x04160100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x030b0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x110c0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x110e0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
ampsca_ampscawrlvl_ampcawrlvlsdllcode(n) = 0x00000200 WrLvlMaxWrDqsSDLLCode = 0x0 WrLvlRunUpdOverride = 0x0 *read-only WrLvlRunUpdWrResult = 0x0 *read-only WrLvlSDLLCode = 0x0
| - | No | -
| Poll ampscawrlvl ampcawrlvlsdllcode FPGA: Skip this step |
Poll: ampscawrlvl_ampcawrlvlsdllcode WrLvlRunUpdWrResult while((CSR(ampsca_ampscawrlvl_ampcawrlvlsdllcode(n)) & 0x200) != 0x0)
| - | No | -

#### 8. AMP Dynamic Address Timing Calibration

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| step8Calibration(0, LPDDR3, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, CA_CALIB, 0, 0, 0, 0, 0, 0, 1, 16, 12); |  | - | - | -
| Program DLL Init and Incr lock timers based on 24 MHz value FPGA: Skip this step |
ampsca_ampscadllctl_dlllocktim(n) = 0x00130013 DllIncLockTim = 0x13 DllInitLockTim = 0x13
| Yes | Yes | -
| Program DLL Init and Incr lock timers based on 24 MHz value FPGA: Skip this step |
ampsdq_ampsdqdllctl_dlllocktim(n) = 0x00130013 DllIncLockTim = 0x13 DllInitLockTim = 0x13
| Yes | Yes | -
| Disable AMP Clock Gating for RunDllUpdt to go through FPGA: Skip this step |
ampsca_ampscagen_ampclk(n) = 0x00100001 FMClkIdleDetectEn = 0x0 *read-only ForceDRAMClkEn = 0x0 *read-only ForceDiv2MClkTopGaterOn = 0x1 ForceFMClkWakeUp = 0x0 *read-only ForceMClkWakeUp = 0x0 *read-only TopClkGateDis = 0x1
| Yes | Yes | -
| Defer SDLL update until frequency change FPGA: Skip this step |
ampsca_ampscasdllctrl_SDLLUpdateDeferEn(n) = 0x00000001 DeferEn = 0x1
| Yes | Yes | -
| Defer SDLL update until frequency change FPGA: Skip this step |
ampsdq_ampsdqsdllctrl_SDLLUpdateDeferEn(n) = 0x00000001 DeferEn = 0x1
| Yes | Yes | -
| Set MDLL override to 0 FPGA: Skip this step |
ampsdq_ampsdqdllctl_MDLLOverride(n) = 0x00010000 MDLLOvrCode = 0x0 MDLLOvrSel = 0x1
| Yes | Yes | -
| Run MDLL update FPGA: Skip this step |
ampsdq_ampsdqdllctl_dllupdtcmd(n) = 0x00000001 RunDllUpdt = 0x0 *read-only
| Yes | Yes | -
| Poll ampsdqdllctl dllupdtcmd FPGA: Skip this step |
Poll: ampsdqdllctl_dllupdtcmd RunDllUpdt while((CSR(ampsdq_ampsdqdllctl_dllupdtcmd(n)) & 0x1) != 0x0)
| Yes | Yes | -
| Enable back AMP Clock Gating for RunDllUpdt to go through FPGA: Skip this step |
ampsca_ampscagen_ampclk(n) = 0x00000000 FMClkIdleDetectEn = 0x0 *read-only ForceDRAMClkEn = 0x0 *read-only ForceDiv2MClkTopGaterOn = 0x0 ForceFMClkWakeUp = 0x0 *read-only ForceMClkWakeUp = 0x0 *read-only TopClkGateDis = 0x0
| Yes | Yes | -
| Program DLL Init and Incr lock timers based on 24 MHz value FPGA: Skip this step |
ampsca_ampscadllctl_dlllocktim(n) = 0x012c012c DllIncLockTim = 0x12c DllInitLockTim = 0x12c
| Yes | Yes | -
| Program DLL Init and Incr lock timers based on 24 MHz value FPGA: Skip this step |
ampsdq_ampsdqdllctl_dlllocktim(n) = 0x012c012c DllIncLockTim = 0x12c DllInitLockTim = 0x12c
| Yes | Yes | -
| RdWrDqCalSegLen_f0 PALLADIUM: Skip this step FPGA: Skip this step |
ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f0(n) = 0x00010002 tRdDqCalSegLen = 0x2 tWrDqCalSegLen = 0x1
| Yes | Yes | -
| RdWrDqCalSegLen_f1 PALLADIUM: Skip this step FPGA: Skip this step |
ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f1(n) = 0x00010002 tRdDqCalSegLen = 0x2 tWrDqCalSegLen = 0x1
| Yes | Yes | -
| FPGA: Skip this step |
amcx_dramcfg_freqchngctl1_freq0(n) = 0x110c110e freqchngmrw2_addr_freq0 = 0xe freqchngmrw2_ctrl_freq0 = 0x0 freqchngmrw2_data_freq0 = 0x11 freqchngmrw3_addr_freq0 = 0xc freqchngmrw3_ctrl_freq0 = 0x0 freqchngmrw3_data_freq0 = 0x11
| Yes | Yes | -
| FPGA: Skip this step |
amcx_dramcfg_freqchngctl1_freq1(n) = 0x110c110e freqchngmrw2_addr_freq1 = 0xe freqchngmrw2_ctrl_freq1 = 0x0 freqchngmrw2_data_freq1 = 0x11 freqchngmrw3_addr_freq1 = 0xc freqchngmrw3_ctrl_freq1 = 0x0 freqchngmrw3_data_freq1 = 0x11
| Yes | Yes | -
| FPGA: Skip this step |
if (platform == FPGA)
amcx_dramcfg_freqchngctl2_freq0(n) = 0xb303000b freqchngmrw4_addr_freq0 = 0xb freqchngmrw4_ctrl_freq0 = 0x0 freqchngmrw4_data_freq0 = 0x0 freqchngmrw5_addr_freq0 = 0x3 freqchngmrw5_ctrl_freq0 = 0x0 freqchngmrw5_data_freq0 = 0xb3
else
amcx_dramcfg_freqchngctl2_freq0(n) = 0xb303440b freqchngmrw4_addr_freq0 = 0xb freqchngmrw4_ctrl_freq0 = 0x0 freqchngmrw4_data_freq0 = 0x44 freqchngmrw5_addr_freq0 = 0x3 freqchngmrw5_ctrl_freq0 = 0x0 freqchngmrw5_data_freq0 = 0xb3
| Yes | Yes | -
| FPGA: Skip this step |
glbtimer_GlbTimer_ZQCTimer = 0x00061a80 ZQCTimerCnt = 0x61a80
| Yes | Yes | -
| HWRdWrDqCalFullScanEnable PALLADIUM: Skip this step FPGA: Skip this step |
ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000003 HWRdDqCalFullScanEnable = 0x1 HWWrDqCalFullScanEnable = 0x1
| Yes | Yes | -

#### 9. Setup registers for DQ calibration for bucket 1

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| Program FSP-WR and FSP-OP to 1 and set VRCG and modified refresh FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0xd80d0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| Yes | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| Yes | No | -
| Wait 1us for FSP setting to take affect. |  | - | - | -
| Program AutoSR FPGA: Skip this step |
amcx_dramcfg_pwrmngten(n) = 0x00000002 AutoSR = 0x1 DynPwrDnEn = 0x0 *read-only McPhyUpdDramClkOff = 0x0 *read-only PwrDnClkOff = 0x0 *read-only SRClkOff = 0x0 *read-only SRExitOpt = 0x0 *read-only
| - | Yes | -
| Program FreqChngMRW Cnt FPGA: Skip this step |
amcx_dramcfg_freqchngctl(n) = 0x00009999 freqchngfspop = 0x0 *read-only freqchngmrwcnt_freq0 = 0x9 freqchngmrwcnt_freq1 = 0x9 freqchngmrwcnt_freq2 = 0x9 freqchngmrwcnt_freq3 = 0x9 freqchngrunsocupd = 0x0 *read-only
| Yes | Yes | -
| WrDqDqsSDLLCtrl FPGA: Skip this step |
ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff00000c WrDqDqsRunSDLLUpd = 0x0 *read-only WrDqDqsRunSDLLUpdOverride = 0x0 *read-only WrDqDqsRunSDLLUpdWrResult = 0x0 *read-only WrDqDqsWrLvlReBalanceEn = 0x1 WrDqSDLLAddHalfClk_f0 = 0x0 *read-only WrDqSDLLAddHalfClk_f1 = 0x0 *read-only WrDqSDLLAddHalfClk_f2 = 0x0 *read-only WrDqSDLLAddHalfClk_f3 = 0x0 *read-only WrDqSDLLHalfClkEn = 0x0 *read-only WrDqSDLLOvrVal = 0x0 WrDqsSDLLOvrVal = 0xff
| Yes | Yes | -
| Re-enable SDLL updates FPGA: Skip this step |
ampsca_ampscasdllctrl_SDLLUpdateDeferEn(n) = 0x00000000 DeferEn = 0x0
| Yes | Yes | -
| Re-enable SDLL updates FPGA: Skip this step |
ampsdq_ampsdqsdllctrl_SDLLUpdateDeferEn(n) = 0x00000000 DeferEn = 0x0
| Yes | Yes | -
| Disable MDLL override FPGA: Skip this step |
ampsdq_ampsdqdllctl_MDLLOverride(n) = 0x00000000 MDLLOvrCode = 0x0 MDLLOvrSel = 0x0
| Yes | Yes | -
| Call custom API provided by PMGR for changing mcu_clk to 800Mhz and mcu_fixed_clk to Mhz // TO BE COMPLETED FPGA: Skip this step |  | - | - | -
|  | - | - | -
| FPGA: Skip this step |
amcx_dramcfg_freqchngctl(n) = 0x00010000 freqchngfspop = 0x0 *read-only freqchngmrwcnt_freq0 = 0x0 freqchngmrwcnt_freq1 = 0x0 freqchngmrwcnt_freq2 = 0x0 freqchngmrwcnt_freq3 = 0x0 freqchngrunsocupd = 0x0 *read-only
| - | No | -
| Poll dramcfg freqchngctl FPGA: Skip this step |
Poll: dramcfg_freqchngctl freqchngrunsocupd while((CSR(amcx_dramcfg_freqchngctl(n)) & 0x10000) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcfg_freqchngctl(n) = 0x00000000 freqchngfspop = 0x0 *read-only freqchngmrwcnt_freq0 = 0x0 freqchngmrwcnt_freq1 = 0x0 freqchngmrwcnt_freq2 = 0x0 freqchngmrwcnt_freq3 = 0x0 freqchngrunsocupd = 0x0 *read-only
| - | No | -
| Wait 2us for the soc update to finish |  | - | - | -

#### 10. AMP Dynamic DQ Calibration

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| step10Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WRLVL, 0, 0, 0, 0, 1, 16, 12); |  | - | - | -
| FPGA: Skip this step |
amph_CFGH_DQS0_WKPUPD(n) = 0x00030788 idle_active_en_f0 = 0x1 idle_active_en_f1 = 0x1 idle_active_en_f2 = 0x0 *read-only idle_active_en_f3 = 0x0 *read-only pdpwk_f0 = 0x0 *read-only pdpwk_f1 = 0x1 pdpwk_f2 = 0x0 *read-only pdpwk_f3 = 0x1 *read-only pupwk_f0 = 0x0 *read-only pupwk_f1 = 0x0 *read-only pupwk_f2 = 0x0 *read-only pupwk_f3 = 0x0 *read-only wkds = 0x7 *read-only
| - | - | -
| FPGA: Skip this step |
amph_CFGH_DQS1_WKPUPD(n) = 0x00030788 idle_active_en_f0 = 0x1 idle_active_en_f1 = 0x1 idle_active_en_f2 = 0x0 *read-only idle_active_en_f3 = 0x0 *read-only pdpwk_f0 = 0x0 *read-only pdpwk_f1 = 0x1 pdpwk_f2 = 0x0 *read-only pdpwk_f3 = 0x1 *read-only pupwk_f0 = 0x0 *read-only pupwk_f1 = 0x0 *read-only pupwk_f2 = 0x0 *read-only pupwk_f3 = 0x0 *read-only wkds = 0x7 *read-only
| - | - | -
| step10Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, RD_DQ_CAL, 0, 0, 0, 0, 1, 16, 12); |  | - | - | -
| step10Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WR_DQ_CAL, 0, 0, 0, 0, 1, 16, 12); |  | - | - | -
| The scale factors for Bin0 and Bin1 WR DQS/DQ skew have to to programmed to the correct values based on board charaterization. Fields are being set to 0 here, since exact board skews are not available now (04/01/14). FPGA: Skip this step |
ampsdq_ampsdqsdllctrl_WrtDQSDQSkewControl(n) = 0x06000000 WrDqDqsIDTVTScaleEn = 0x1 *read-only WrDqDqsMDLLVTScaleEn = 0x1 *read-only WrtDQSDQScaleFactorF0 = 0x0 WrtDQSDQScaleFactorF1 = 0x0 WrtDQSDQScaleFactorPlusSel = 0x0
| - | - | -

#### 11. Setup registers for CA calibration for bucket 0

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| FPGA: Skip this step |
amph_CFGH_DQS0_WKPUPD(n) = 0x00000788 idle_active_en_f0 = 0x0 idle_active_en_f1 = 0x0 idle_active_en_f2 = 0x0 *read-only idle_active_en_f3 = 0x0 *read-only pdpwk_f0 = 0x0 *read-only pdpwk_f1 = 0x1 pdpwk_f2 = 0x0 *read-only pdpwk_f3 = 0x1 *read-only pupwk_f0 = 0x0 *read-only pupwk_f1 = 0x0 *read-only pupwk_f2 = 0x0 *read-only pupwk_f3 = 0x0 *read-only wkds = 0x7 *read-only
| - | No | -
| FPGA: Skip this step |
amph_CFGH_DQS1_WKPUPD(n) = 0x00000788 idle_active_en_f0 = 0x0 idle_active_en_f1 = 0x0 idle_active_en_f2 = 0x0 *read-only idle_active_en_f3 = 0x0 *read-only pdpwk_f0 = 0x0 *read-only pdpwk_f1 = 0x1 pdpwk_f2 = 0x0 *read-only pdpwk_f3 = 0x1 *read-only pupwk_f0 = 0x0 *read-only pupwk_f1 = 0x0 *read-only pupwk_f2 = 0x0 *read-only pupwk_f3 = 0x0 *read-only wkds = 0x7 *read-only
| - | No | -
| Program FSP-WR to 0 and FSP-OP to 1 and set VRCG and modified refresh FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x980d0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Configure DRAM MR2 register (latency) through MRR/MRW command registers. The example shows the nominal programming for LPDDR2-1066 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices. FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x24020100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Configure DRAM MR1 register through MRR/MRW command registers. This includes the following: WC=Wrap BT=Sequential BL=BL16. nWR, the example shows the nominal programming for LPDDR3- 1600 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices. FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0xce010100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0xb3030100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x04160100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x440b0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x110c0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x110e0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -

#### 12. AMP Dynamic Address Timing Calibration

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| step12Calibration(0, LPDDR3, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, CA_CALIB, 0, 0, 0, 0, 0, 0, 0, 24, 12); |  | - | - | -
| FPGA: Skip this step SAMSUNG: Perform this step |
amcx_dramcmd_mrinitcmd(n) = 0x340b0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step SAMSUNG: Perform this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Issue DRAM ZQ calibration START MPC command MRINIT CMD registers SAMSUNG: Perform this step |
amcx_dramcmd_mrinitcmd(n) = 0x4f004100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd SAMSUNG: Perform this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Wait 1us for tZQCAL. |  | - | - | -
| Issue DRAM ZQ calibration LATCH MPC command MRINIT CMD registers SAMSUNG: Perform this step |
amcx_dramcmd_mrinitcmd(n) = 0x51004100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd SAMSUNG: Perform this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Wait 20ns for tZQLAT. |  | - | - | -
| SAMSUNG: Perform this step |
amcx_dramcfg_freqchngctl2_freq0(n) = 0xb303340b freqchngmrw4_addr_freq0 = 0xb freqchngmrw4_ctrl_freq0 = 0x0 freqchngmrw4_data_freq0 = 0x34 freqchngmrw5_addr_freq0 = 0x3 freqchngmrw5_ctrl_freq0 = 0x0 freqchngmrw5_data_freq0 = 0xb3
| - | No | -

#### 13. Setup registers for DQ calibration for bucket 0

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| Program FSP-WR and FSP-OP to 0 and set VRCG and modified refresh FPGA: Skip this step |
amcx_dramcmd_mrinitcmd(n) = 0x180d0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd FPGA: Skip this step |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Wait 1us for FSP setting to take affect. |  | - | - | -
| Call custom API provided by PMGR for changing mcu_clk to 1200Mhz and mcu_fixed_clk to Mhz // TO BE COMPLETED FPGA: Skip this step |  | - | - | -
|  | - | - | -
| FPGA: Skip this step |
amcx_dramcfg_freqchngctl(n) = 0x00010000 freqchngfspop = 0x0 *read-only freqchngmrwcnt_freq0 = 0x0 freqchngmrwcnt_freq1 = 0x0 freqchngmrwcnt_freq2 = 0x0 freqchngmrwcnt_freq3 = 0x0 freqchngrunsocupd = 0x0 *read-only
| - | No | -
| Poll dramcfg freqchngctl FPGA: Skip this step |
Poll: dramcfg_freqchngctl freqchngrunsocupd while((CSR(amcx_dramcfg_freqchngctl(n)) & 0x10000) != 0x0)
| - | No | -
| FPGA: Skip this step |
amcx_dramcfg_freqchngctl(n) = 0x00000000 freqchngfspop = 0x0 *read-only freqchngmrwcnt_freq0 = 0x0 freqchngmrwcnt_freq1 = 0x0 freqchngmrwcnt_freq2 = 0x0 freqchngmrwcnt_freq3 = 0x0 freqchngrunsocupd = 0x0 *read-only
| - | No | -
| Wait 2us for the soc update to finish |  | - | - | -

#### 14. AMP Dynamic DQ Calibration

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WRLVL, 0, 0, 0, 0, 0, 24, 12); |  | - | - | -
| FPGA: Skip this step |
amph_CFGH_DQS0_WKPUPD(n) = 0x00030788 idle_active_en_f0 = 0x1 idle_active_en_f1 = 0x1 idle_active_en_f2 = 0x0 *read-only idle_active_en_f3 = 0x0 *read-only pdpwk_f0 = 0x0 *read-only pdpwk_f1 = 0x1 pdpwk_f2 = 0x0 *read-only pdpwk_f3 = 0x1 *read-only pupwk_f0 = 0x0 *read-only pupwk_f1 = 0x0 *read-only pupwk_f2 = 0x0 *read-only pupwk_f3 = 0x0 *read-only wkds = 0x7 *read-only
| - | No | -
| FPGA: Skip this step |
amph_CFGH_DQS1_WKPUPD(n) = 0x00030788 idle_active_en_f0 = 0x1 idle_active_en_f1 = 0x1 idle_active_en_f2 = 0x0 *read-only idle_active_en_f3 = 0x0 *read-only pdpwk_f0 = 0x0 *read-only pdpwk_f1 = 0x1 pdpwk_f2 = 0x0 *read-only pdpwk_f3 = 0x1 *read-only pupwk_f0 = 0x0 *read-only pupwk_f1 = 0x0 *read-only pupwk_f2 = 0x0 *read-only pupwk_f3 = 0x0 *read-only wkds = 0x7 *read-only
| - | No | -
| step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, RD_DQ_CAL, 0, 0, 0, 0, 0, 24, 12); |  | - | - | -
| step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WR_DQ_CAL, 0, 0, 0, 0, 0, 24, 12); |  | - | - | -

#### 15. Setup registers for boot.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
amph_CFGH_DEBUG_SPARE0(n) = 0x0000040e control = 0x40e
| - | - | -
| Program FSP-WR to 1 and FSP-OP to 0 and reset VRCG, since all calibrations are done |
amcx_dramcmd_mrinitcmd(n) = 0x500d0100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | No | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | No | -
| Wait 1us for FSP setting to take affect. |  | - | - | -
| Program FreqChngMRW Cnt |
amcx_dramcfg_freqchngctl(n) = 0x00009999 freqchngfspop = 0x0 *read-only freqchngmrwcnt_freq0 = 0x9 freqchngmrwcnt_freq1 = 0x9 freqchngmrwcnt_freq2 = 0x9 freqchngmrwcnt_freq3 = 0x9 freqchngrunsocupd = 0x0 *read-only
| - | No | -
ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000008 WrDqDqsRunSDLLUpd = 0x0 *read-only WrDqDqsRunSDLLUpdOverride = 0x0 *read-only WrDqDqsRunSDLLUpdWrResult = 0x0 *read-only WrDqDqsWrLvlReBalanceEn = 0x1 WrDqSDLLAddHalfClk_f0 = 0x0 *read-only WrDqSDLLAddHalfClk_f1 = 0x0 *read-only WrDqSDLLAddHalfClk_f2 = 0x0 *read-only WrDqSDLLAddHalfClk_f3 = 0x0 *read-only WrDqSDLLHalfClkEn = 0x0 *read-only WrDqSDLLOvrVal = 0x0 WrDqsSDLLOvrVal = 0xff
| - | No | -
| DO_CALIBRATION: Skip this step |
ampsdq_ampsdqsdllctrl_rd0sdllctrl(n) = 0x001a0004 Rd0RunSDLLUpd = 0x0 *read-only Rd0RunSDLLUpdOverride = 0x0 *read-only Rd0RunSDLLUpdWrResult = 0x0 *read-only Rd0SDLLOvrVal = 0x1a
| - | No | -
| Poll ampsdqsdllctrl rd0sdllctrl DO_CALIBRATION: Skip this step |
Poll: ampsdqsdllctrl_rd0sdllctrl Rd0RunSDLLUpdWrResult while((CSR(ampsdq_ampsdqsdllctrl_rd0sdllctrl(n)) & 0x4) != 0x0)
| - | No | -
| PALLADIUM: Skip this step |
ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000000 HWRdDqCalFullScanEnable = 0x0 HWWrDqCalFullScanEnable = 0x0
| - | - | -
| PALLADIUM: Skip this step |
ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000003 HWRdDqCalFullScanEnable = 0x1 HWWrDqCalFullScanEnable = 0x1
| - | - | -

#### 16. Enable other features

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| Turn on the freq change waiting for refresh and self-refresh exit feature |
amcx_dramcfg_arefparam(n) = 0x08010019 FreqChngWaitThr = 0x1 *read-only PhyUpdWaitRefresh = 0x1 PhyUpdWaitThr = 0x1 *read-only PhyUpdWaittXSR = 0x0 RefAssertCnt = 0x8 SRExitRefCnt = 0x1
| - | - | -
| Enable periodic ZQC. (Optional) Note the ZqCalIntrvl setting shown here is based on tREFI=3.9us and the target interval is ~128ms (max supported value). The actual setting may vary depending on the DRAM and the system. |
if (platform == FPGA)
amcx_dramcfg_odtszqc(n) = 0xc0000000 DerateParamSRExit = 0x0 OdtsRdIntrvl = 0x0 SRExitZQCChnlQuiet = 0x1 ShareZQRes = 0x0 TempDrtEn = 0x0 ZQCChnlQuiet = 0x0 *read-only ZQCStack = 0x1 ZqCalIntrvl = 0x0
else
amcx_dramcfg_odtszqc(n) = 0xc0001000 DerateParamSRExit = 0x0 OdtsRdIntrvl = 0x0 SRExitZQCChnlQuiet = 0x1 ShareZQRes = 0x0 TempDrtEn = 0x1 ZQCChnlQuiet = 0x0 *read-only ZQCStack = 0x1 ZqCalIntrvl = 0x0
| - | - | -
| Turn on the QBR enables. |
amcx_mcusch_qbren(n) = 0x0000000d ErlyQbrEn = 0x1 LateQbrEn = 0x1 MifQbrEn = 0x1 PredictiveM2AReq = 0x0 *read-only
| - | - | -
amcx_dramcfg_arefen_freq3(n) = 0x11100000 ARpbEn_freq3 = 0x0 HiTempRefRnkAgeOut_freq3 = 0x1 RefCntrHiWaterMark_freq3 = 0x1 RefCntrLoWaterMark_freq3 = 0x1
| - | No | -
amcx_dramcfg_arefen_freq2(n) = 0x11000000 ARpbEn_freq2 = 0x0 HiTempRefRnkAgeOut_freq2 = 0x0 RefCntrHiWaterMark_freq2 = 0x1 RefCntrLoWaterMark_freq2 = 0x1
| - | No | -
amcx_dramcfg_arefen_freq1(n) = 0x11110000 ARpbEn_freq1 = 0x1 HiTempRefRnkAgeOut_freq1 = 0x1 RefCntrHiWaterMark_freq1 = 0x1 RefCntrLoWaterMark_freq1 = 0x1
| - | No | -
| Turn on auto refresh. |
amcx_dramcfg_arefen_freq0(n) = 0x1111013f ARpbEn_freq0 = 0x1 AutoRefEn = 0x1 AutoRefSchEn = 0x1 DisableHiTempREFab = 0x1 EarlyCasAgeOut = 0x0 HiPriREFpbPch = 0x1 HiTempRefRnkAgeOut_freq0 = 0x1 REFpb2bank = 0x0 REFpbEarlyPch = 0x1 RefCntrHiWaterMark_freq0 = 0x1 RefCntrLoWaterMark_freq0 = 0x1 RefOpptEn = 0x1 tREFBWREFpb = 0x1
| - | No | -
amph_CFGH_B0_DYN_ISEL_ASRTIME(n) = 0x00001117 rcvr_minisel_assrttime_f0 = 0x17 rcvr_minisel_assrttime_f1 = 0x11 rcvr_minisel_assrttime_f2 = 0x0 *read-only rcvr_minisel_assrttime_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_B0_DYN_ISEL(n) = 0x00000003 dyn_isel_ctrl_en_f0 = 0x1 dyn_isel_ctrl_en_f1 = 0x1 dyn_isel_ctrl_en_f2 = 0x0 *read-only dyn_isel_ctrl_en_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_B1_DYN_ISEL(n) = 0x00000003 dyn_isel_ctrl_en_f0 = 0x1 dyn_isel_ctrl_en_f1 = 0x1 dyn_isel_ctrl_en_f2 = 0x0 *read-only dyn_isel_ctrl_en_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_DQS0_DCD_IOCTL(n) = 0x00030000 dcdi = 0x0 *read-only dcdo = 0x0 *read-only dyn_isel_ctrl_en_f0 = 0x1 dyn_isel_ctrl_en_f1 = 0x1 dyn_isel_ctrl_en_f2 = 0x0 *read-only dyn_isel_ctrl_en_f3 = 0x0 *read-only
| - | - | -
amph_CFGH_DQS1_DCD_IOCTL(n) = 0x00030000 dcdi = 0x0 *read-only dcdo = 0x0 *read-only dyn_isel_ctrl_en_f0 = 0x1 dyn_isel_ctrl_en_f1 = 0x1 dyn_isel_ctrl_en_f2 = 0x0 *read-only dyn_isel_ctrl_en_f3 = 0x0 *read-only
| - | - | -

#### 17. Enable the Fast Critical Word Forwarding feature (optional)

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| Configure the MIF FCWF pull- in cycles. (Here we just use 0x8 as an example, please refer to register description for the valid programming range and refer to performance simulation results) |
if (platform == PALLADIUM)
amcx_mcusch_qbrparam(n) = 0x61616161 RdCwfEarlyCyc_freq0 = 0x1 RdCwfEarlyCyc_freq1 = 0x1 RdCwfEarlyCyc_freq2 = 0x1 RdCwfEarlyCyc_freq3 = 0x1 RdRemEarlyCyc_freq0 = 0x6 RdRemEarlyCyc_freq1 = 0x6 RdRemEarlyCyc_freq2 = 0x6 RdRemEarlyCyc_freq3 = 0x6
else if (platform == FPGA)
amcx_mcusch_qbrparam(n) = 0x00006100 RdCwfEarlyCyc_freq0 = 0x0 RdCwfEarlyCyc_freq1 = 0x1 RdCwfEarlyCyc_freq2 = 0x0 RdCwfEarlyCyc_freq3 = 0x0 RdRemEarlyCyc_freq0 = 0x0 RdRemEarlyCyc_freq1 = 0x6 RdRemEarlyCyc_freq2 = 0x0 RdRemEarlyCyc_freq3 = 0x0
else
amcx_mcusch_qbrparam(n) = 0x000061a5 RdCwfEarlyCyc_freq0 = 0x5 RdCwfEarlyCyc_freq1 = 0x1 RdCwfEarlyCyc_freq2 = 0x0 RdCwfEarlyCyc_freq3 = 0x0 RdRemEarlyCyc_freq0 = 0xa RdRemEarlyCyc_freq1 = 0x6 RdRemEarlyCyc_freq2 = 0x0 RdRemEarlyCyc_freq3 = 0x0
| - | - | -
| Turn on the PredictiveM2AReq feature in MIF. (The other Qbr enables are turned on here, but not related to CWF feature) |
if (platform == PALLADIUM)
amcx_mcusch_qbren(n) = 0x0000000d ErlyQbrEn = 0x1 LateQbrEn = 0x1 MifQbrEn = 0x1 PredictiveM2AReq = 0x0
else
amcx_mcusch_qbren(n) = 0x0000000f ErlyQbrEn = 0x1 LateQbrEn = 0x1 MifQbrEn = 0x1 PredictiveM2AReq = 0x1
| - | - | -
| Poll mcccfg MccPwrOnWayCntStatus |
Poll: mcccfg_MccPwrOnWayCntStatus Mcc0CurDatWayOnCnt Mcc0CurWayCnt Mcc0TgtWayCnt Mcc1CurDatWayOnCnt Mcc1CurWayCnt Mcc1TgtWayCnt while((CSR(amcc_mcccfg_MccPwrOnWayCntStatus) & 0x7fff7fff) != 0x42104210)
| - | - | -
amcc_amccperfcntr_Mcc0QPropCtrl = 0x300011a2 Mcc0AfCacheRdPropQCmd = 0x1 *read-only Mcc0AfCacheRdPropQTrakEnbl = 0x0 *read-only Mcc0AfDramRdPropQCmd = 0x1 *read-only Mcc0AfDramRdPropQTrakEnbl = 0x0 *read-only Mcc0DpPropQCfg = 0x0 *read-only Mcc0DpPropQCmd = 0x1 *read-only Mcc0DpPropQTrakEnbl = 0x0 *read-only Mcc0MsqQPropCfg = 0x0 *read-only Mcc0MsqQPropQCmd = 0x0 *read-only Mcc0MsqQPropTrakEnbl = 0x0 *read-only Mcc0QpropOutSel = 0x3 Mcc0TpPropQCmd = 0x0 *read-only Mcc0TpPropQTrakEnbl = 0x1 Mcc0TpQPropSel = 0x4 Mcc0TpQpropMask = 0x0 *read-only
| - | - | -
amcc_amccperfcntr_Mcc1QPropCtrl = 0x300011a2 Mcc1AfCacheRdPropQCmd = 0x1 *read-only Mcc1AfCacheRdPropQTrakEnbl = 0x0 *read-only Mcc1AfDramRdPropQCmd = 0x1 *read-only Mcc1AfDramRdPropQTrakEnbl = 0x0 *read-only Mcc1DpPropQCfg = 0x0 *read-only Mcc1DpPropQCmd = 0x1 *read-only Mcc1DpPropQTrakEnbl = 0x0 *read-only Mcc1MsqQPropCfg = 0x0 *read-only Mcc1MsqQPropQCmd = 0x0 *read-only Mcc1MsqQPropTrakEnbl = 0x0 *read-only Mcc1QpropOutSel = 0x3 Mcc1TpPropQCmd = 0x0 *read-only Mcc1TpPropQTrakEnbl = 0x1 Mcc1TpQPropSel = 0x4 Mcc1TpQpropMask = 0x0 *read-only
| - | - | -
amcc_mcccfg_MccGen = 0x00000126 DramAccessEn = 0x1 EccEn = 0x1 *read-only HitBypassEcc = 0x0 *read-only MccEn = 0x0 *read-only MccRamEn = 0x1 *read-only MccRamEnLock = 0x0 *read-only MccStop = 0x0 *read-only SpecRdEn = 0x0 *read-only SpecRdNum = 0x1 *read-only
| - | - | -

#### 18. Enable Power & ClockGating features and Configure the MCC and Global Timer

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| Enable AMPCA Fixed MCLK Clock Gating |
ampsca_ampscagen_ampclk(n) = 0x00000000 FMClkIdleDetectEn = 0x0 ForceDRAMClkEn = 0x0 *read-only ForceDiv2MClkTopGaterOn = 0x0 ForceFMClkWakeUp = 0x0 ForceMClkWakeUp = 0x0 TopClkGateDis = 0x0
| - | - | -
| Enable AMPDQ Fixed MCLK Clock Gating |
ampsdq_ampsdqgen_ampclk(n) = 0x00000000 FMClkIdleDetectEn = 0x0 ForceDRAMClkEn = 0x0 *read-only ForceDiv2MClkTopGaterOn = 0x0 *read-only ForceFMClkWakeUp = 0x0 ForceMClkWakeUp = 0x0 TopClkGateDis = 0x0
| - | - | -
| disable dynamic power-down. |
amcx_dramcfg_pwrmngten(n) = 0x00000132 AutoSR = 0x1 DynPwrDnEn = 0x0 McPhyUpdDramClkOff = 0x0 PwrDnClkOff = 0x1 SRClkOff = 0x1 SRExitOpt = 0x1
| - | - | -
| disable dynamic power-down. |
amcx_dramcfg_pwrmngten(n) = 0x00000133 AutoSR = 0x1 DynPwrDnEn = 0x1 McPhyUpdDramClkOff = 0x0 PwrDnClkOff = 0x1 SRClkOff = 0x1 SRExitOpt = 0x1
| - | No | -
| Revert auto self-refresh wait timer to guided value. FPGA: Skip this step |
amcx_dramcfg_pwrmngtparam_freq0(n) = 0x01800000 BypsPwrDnDlyCyc_freq0 = 0x0 *read-only SelfRefTmrVal_freq0 = 0x180
| - | - | -
| Setting WqAgeOutVal to be 3/4 of SelfRefTmrVal, to flush writes in a reasonable time. FPGA: Skip this step |
amcx_mcusch_psqwqctl1(n) = 0x01640120 WqAgeOutVal_freq0 = 0x120 WqAgeOutVal_freq1 = 0x164 *read-only
| - | - | -
| Enable wakeups from glbl timer to pmgr |
glbtimer_GlbTimer_PmgrWakeUpCfg = 0x000000ff FreqChngEn = 0x1 IdtEn = 0x1 ImpCalEn = 0x1 MdllEn = 0x1 RdCalEn = 0x1 VoltRampEn = 0x1 WrCalEn = 0x1 ZQCalEn = 0x1
| Yes | - | -
glbtimer_GlbTimer_PreFreq2AllBankDly0 = 0x01500150 PreFreqChng2AllBankDly_f0 = 0x150 PreFreqChng2AllBankDly_f1 = 0x150
| - | - | -
glbtimer_GlbTimer_PreFreq2AllBankDly1 = 0x01500150 PreFreqChng2AllBankDly_f2 = 0x150 PreFreqChng2AllBankDly_f3 = 0x150
| - | - | -
glbtimer_GlbTimer_PreFreqChng2FreqChngDly0 = 0x02a002a0 PreFreqChng2FreqChngDly_f0 = 0x2a0 PreFreqChng2FreqChngDly_f1 = 0x2a0
| - | - | -
glbtimer_GlbTimer_PreFreqChng2FreqChngDly1 = 0x02a002a0 PreFreqChng2FreqChngDly_f2 = 0x2a0 PreFreqChng2FreqChngDly_f3 = 0x2a0
| - | - | -
glbtimer_GlbTimer_Cal2PreFreqChngDly0 = 0x00900090 Cal2PreFreqChngDly_f0 = 0x90 Cal2PreFreqChngDly_f1 = 0x90
| - | - | -
glbtimer_GlbTimer_Cal2PreFreqChngDly1 = 0x00900090 Cal2PreFreqChngDly_f2 = 0x90 Cal2PreFreqChngDly_f3 = 0x90
| - | - | -
glbtimer_GlbTimer_FreqChng2PstCalDly0 = 0x01200120 FreqChng2PstCalDly_f0 = 0x120 FreqChng2PstCalDly_f1 = 0x120
| - | - | -
glbtimer_GlbTimer_FreqChng2PstCalDly1 = 0x01200120 FreqChng2PstCalDly_f2 = 0x120 FreqChng2PstCalDly_f3 = 0x120
| - | - | -
glbtimer_GlbTimer_MdllTimer = 0x00000bb8 MdllTimerCnt = 0xbb8
| Yes | - | -
glbtimer_GlbTimer_MdllVoltRampTimer = 0x0000004b MdllVoltRampTimerCnt = 0x4b
| Yes | - | -
glbtimer_GlbTimer_CtrlUpdMaskTimer = 0x0000000f CtrlUpdMaskTimerCnt = 0xf
| Yes | - | -
glbtimer_GlbTimer_RdCalTimer = 0x002dc6c0 RdCalTimerCnt = 0x2dc6c0
| Yes | - | -
glbtimer_GlbTimer_WrCalTimer = 0x002dc6c0 WrCalTimerCnt = 0x2dc6c0
| Yes | - | -
| SAMSUNG: Skip this step |
glbtimer_GlbTimer_ZQCTimer = 0x003d0900 ZQCTimerCnt = 0x3d0900
| Yes | No | -
glbtimer_GlbTimer_PerCal_FreqChngTimer = 0x000493e0 PerCal_FreqChngTimerCnt = 0x493e0
| Yes | No | -
glbtimer_GlbTimer_VoltRampTimer = 0x000493e0 VoltRampTimerCnt = 0x493e0
| Yes | No | -
glbtimer_GlbTimer_ImpCalTimer = 0x00002ee0 ImpCalTimerCnt = 0x2ee0
| Yes | No | -
glbtimer_GlbTimer_VoltRamp2AllBankDly0 = 0x00d800d8 VoltRamp2AllBankDly_f0 = 0xd8 VoltRamp2AllBankDly_f1 = 0xd8
| Yes | No | -
glbtimer_GlbTimer_VoltRamp2AllBankDly1 = 0x00d800d8 VoltRamp2AllBankDly_f2 = 0xd8 VoltRamp2AllBankDly_f3 = 0xd8
| Yes | No | -
glbtimer_GlbTimer_AllBank2PmgrAckDly0 = 0x00900090 AllBank2PmgrAckDly_f0 = 0x90 AllBank2PmgrAckDly_f1 = 0x90
| Yes | No | -
glbtimer_GlbTimer_AllBank2PmgrAckDly1 = 0x00900090 AllBank2PmgrAckDly_f2 = 0x90 AllBank2PmgrAckDly_f3 = 0x90
| Yes | No | -
| Dynamic clk pwr gating reg |
amcx_amcgen_amcclkpwrgate(n) = 0x050a0000 ClkPwrWaitCyc = 0xa *read-only MCUBCGClkGateEn = 0x0 *read-only MCUBCGPwrGateEn = 0x0 *read-only PwrRstCyc = 0x5 *read-only
| - | - | -

#### 19. Do a ODTS read and set ODTS interval so MR4 on-die temperature sensor read occurs periodically.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
| Perform an MRR to DRAM mode register MR4 to establish a base value for ODTS reading. Another intention is to bring DRAM out of self-refresh. Done in both cold boot and resume boot. |
amcx_dramcmd_mrinitcmd(n) = 0x50041100 MRCmdAddr = 0x0 *read-only MRCmdCs = 0x0 *read-only MRCmdData = 0x0 *read-only MRCmdIsMPC = 0x0 *read-only MRCmdIsRd = 0x0 *read-only RunMRCmd = 0x0 *read-only RunRdLvl = 0x0 *read-only RunSRExit = 0x0 *read-only
| - | - | -
| Poll dramcmd mrinitcmd |
Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)
| - | - | -
| Enable periodic ODTS and temperature based refresh rate modulation. (Optional) Note the OdtsRdIntrvl setting shown here is based on tREFI=3.9us and the target interval is ~100. The actual setting may vary depending on the DRAM and the system. Palladium: this step is skipped, ODTS is not supported PALLADIUM: Skip this step |
if (platform == FPGA)
amcx_dramcfg_odtszqc(n) = 0xc0002320 DerateParamSRExit = 0x1 OdtsRdIntrvl = 0x320 SRExitZQCChnlQuiet = 0x1 ShareZQRes = 0x0 TempDrtEn = 0x0 ZQCChnlQuiet = 0x0 *read-only ZQCStack = 0x1 ZqCalIntrvl = 0x0
else
amcx_dramcfg_odtszqc(n) = 0xc0003320 DerateParamSRExit = 0x1 OdtsRdIntrvl = 0x320 SRExitZQCChnlQuiet = 0x1 ShareZQRes = 0x0 TempDrtEn = 0x1 ZQCChnlQuiet = 0x0 *read-only ZQCStack = 0x1 ZqCalIntrvl = 0x0
| - | - | -

#### Mcc Cache Initialization. This section is not part of the essential init sequence. This should be run when the system is done using the CacheAsRam

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---
amcc_mcccfg_MccGen = 0x00000124 DramAccessEn = 0x1 EccEn = 0x1 *read-only HitBypassEcc = 0x0 *read-only MccEn = 0x0 *read-only MccRamEn = 0x0 MccRamEnLock = 0x0 *read-only MccStop = 0x0 *read-only SpecRdEn = 0x0 *read-only SpecRdNum = 0x1 *read-only
| - | - | -
| Program AF Allocation Hints, allocation does not happen unless there is a hint as the generic allocation policy |
amcc_mcccfg_MccAlcHint = 0x00001110 MccAlcHintEn = 0x1 MccGenericAlc = 0x0 *read-only MccSclDtyEn = 0x1 MccStickyEn = 0x1
| - | - | -
| Poll mcccfg MccPwrOnWayCntStatus |
Poll: mcccfg_MccPwrOnWayCntStatus Mcc0CurDatWayOnCnt Mcc0CurWayCnt Mcc0TgtWayCnt Mcc1CurDatWayOnCnt Mcc1CurWayCnt Mcc1TgtWayCnt while((CSR(amcc_mcccfg_MccPwrOnWayCntStatus) & 0x7fff7fff) != 0x42104210)
| - | - | -
| Maximum Number of Powered Ways. |
amcc_mcccfg_MccPwrOnWayCntCtrl = 0x00000110 MccMaxWayOnCnt = 0x10 MccMaxWayOnExact = 0x1 *read-only
| - | - | -
| Turn on the MCC |
amcc_mcccfg_MccGen = 0x00000195 DramAccessEn = 0x1 EccEn = 0x1 *read-only HitBypassEcc = 0x0 *read-only MccEn = 0x1 MccRamEn = 0x0 MccRamEnLock = 0x0 *read-only MccStop = 0x0 *read-only SpecRdEn = 0x1 SpecRdNum = 0x4
| - | - | -
| Set Dynamic Way PowerGating |
amcc_mcccfg_MccPwrOnWayCntCtrl = 0x00000010 MccMaxWayOnCnt = 0x10 MccMaxWayOnExact = 0x0
| - | - | -